A spread spectrum clock generator for displayPort main link

This brief presents a spread spectrum clock generator (SSCG) with a process variation compensator for DisplayPort main link. The process variation compensator reduces the error of spread ratio and guarantees reliable operation of an SSCG. The test chip has been implemented in 0.18-μ complementary metaloxidesemiconductor process. The SSCG supports 10-phase 270- and 162-MHz clocks. The phase noise of an output clock at 270 MHz without spread spectrum clocking is -97.7 and - 120.4 dBc/Hz at 1- and 10-MHz offset, respectively. The peak reduction is 8.75 dBm, and the spread ratio of 5000 ppm is achieved with a process variation compensator.