@inproceedings{17862342ad824308a4575fef4d9fdc93,
title = "A standard CMOS neural stimulator IC with high voltage compliant output current driver",
abstract = "This paper presents a 180nm CMOS biphasic neural stimulator integrated circuit for implantable prosthetic devices. The proposed stimulator has the ability to deliver up to 1-mA of well-matched biphasic current through 10-kΩ load using 12.8 V supply voltage. A voltage compliance of 11.5 V is achieved by utilizing a cascode current-mirror output driver topology. In order to allow standard CMOS working at high voltage, transistor stacking and dynamic gate biasing techniques are used. In addition, an active charge balancing circuit is utilized for maintaining zero net charge when a stimulation cycle is complete.",
keywords = "Active charge balancing, Dynamic biasing, High-voltage, Neural stimulation, Transistor stacking",
author = "Tuan, \{Vo Nhut\} and Cha, \{Hyouk Kyu\}",
note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 14th International SoC Design Conference, ISOCC 2017 ; Conference date: 05-11-2017 Through 08-11-2017",
year = "2018",
month = may,
day = "29",
doi = "10.1109/ISOCC.2017.8368915",
language = "English",
series = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "316--317",
booktitle = "Proceedings - International SoC Design Conference 2017, ISOCC 2017",
}