A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

Young Chul Cho; Yong Cheol Bae; Byoung Mo Moon; Yoon Joo Eom; Min Su Ahn; Won Young Lee; Cheong Ryong Cho; Min Ho Park; Young Jin Jeon; Jin Oh Ahn; Baek Kyu Choi; Dan Kyu Kang; Sang Hyuk Yoon; Yun Seok Yang; Kwang Il Park; Jung Hwan Choi; Jung Bae Lee; Joo Sun Choi

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

Young Chul Cho, Yong Cheol Bae, Byoung Mo Moon, Yoon Joo Eom, Min Su Ahn, Won Young Lee, Cheong Ryong Cho, Min Ho Park, Young Jin Jeon, Jin Oh Ahn, Baek Kyu Choi, Dan Kyu Kang, Sang Hyuk Yoon, Yun Seok Yang, Kwang Il Park, Jung Hwan Choi, Jung Bae Lee, Joo Sun Choi

Media IT Engineering Program

Samsung

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

21 Scopus citations

Abstract

A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented. Power efficiency is 2.4mW/Gbps/pin in 20nm mobile DRAM process, which is 44% lower value than that of LPDDR3.

Original language	English
Title of host publication	2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers
Pages	C240-C241
State	Published - 2013
Event	2013 Symposium on VLSI Circuits, VLSIC 2013 - Kyoto, Japan Duration: 12 Jun 2013 → 14 Jun 2013

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference	2013 Symposium on VLSI Circuits, VLSIC 2013
Country/Territory	Japan
City	Kyoto
Period	12/06/13 → 14/06/13

Cite this

Cho, Y. C., Bae, Y. C., Moon, B. M., Eom, Y. J., Ahn, M. S., Lee, W. Y., Cho, C. R., Park, M. H., Jeon, Y. J., Ahn, J. O., Choi, B. K., Kang, D. K., Yoon, S. H., Yang, Y. S., Park, K. I., Choi, J. H., Lee, J. B., & Choi, J. S. (2013). A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers (pp. C240-C241). Article 6578678 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

@inproceedings{f3f12c154027458e9d0de806c323a036,

title = "A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application",

abstract = "A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented. Power efficiency is 2.4mW/Gbps/pin in 20nm mobile DRAM process, which is 44\% lower value than that of LPDDR3.",

author = "Cho, \{Young Chul\} and Bae, \{Yong Cheol\} and Moon, \{Byoung Mo\} and Eom, \{Yoon Joo\} and Ahn, \{Min Su\} and Lee, \{Won Young\} and Cho, \{Cheong Ryong\} and Park, \{Min Ho\} and Jeon, \{Young Jin\} and Ahn, \{Jin Oh\} and Choi, \{Baek Kyu\} and Kang, \{Dan Kyu\} and Yoon, \{Sang Hyuk\} and Yang, \{Yun Seok\} and Park, \{Kwang Il\} and Choi, \{Jung Hwan\} and Lee, \{Jung Bae\} and Choi, \{Joo Sun\}",

year = "2013",

language = "English",

isbn = "9784863483484",

series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

pages = "C240--C241",

booktitle = "2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers",

note = "2013 Symposium on VLSI Circuits, VLSIC 2013 ; Conference date: 12-06-2013 Through 14-06-2013",

}

Cho, YC, Bae, YC, Moon, BM, Eom, YJ, Ahn, MS, Lee, WY, Cho, CR, Park, MH, Jeon, YJ, Ahn, JO, Choi, BK, Kang, DK, Yoon, SH, Yang, YS, Park, KI, Choi, JH, Lee, JB & Choi, JS 2013, A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application. in 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers., 6578678, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, pp. C240-C241, 2013 Symposium on VLSI Circuits, VLSIC 2013, Kyoto, Japan, 12/06/13.

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application. / Cho, Young Chul; Bae, Yong Cheol; Moon, Byoung Mo et al.
2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. p. C240-C241 6578678 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Cho, Young Chul

AU - Bae, Yong Cheol

AU - Moon, Byoung Mo

AU - Eom, Yoon Joo

AU - Ahn, Min Su

AU - Lee, Won Young

AU - Cho, Cheong Ryong

AU - Park, Min Ho

AU - Jeon, Young Jin

AU - Ahn, Jin Oh

AU - Choi, Baek Kyu

AU - Kang, Dan Kyu

AU - Yoon, Sang Hyuk

AU - Yang, Yun Seok

AU - Park, Kwang Il

AU - Choi, Jung Hwan

AU - Lee, Jung Bae

AU - Choi, Joo Sun

PY - 2013

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N2 - A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented. Power efficiency is 2.4mW/Gbps/pin in 20nm mobile DRAM process, which is 44% lower value than that of LPDDR3.

AB - A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented. Power efficiency is 2.4mW/Gbps/pin in 20nm mobile DRAM process, which is 44% lower value than that of LPDDR3.

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SN - 9784863483484

T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

SP - C240-C241

BT - 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers

T2 - 2013 Symposium on VLSI Circuits, VLSIC 2013

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Cho YC, Bae YC, Moon BM, Eom YJ, Ahn MS, Lee WY et al. A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application. In 2013 Symposium on VLSI Circuits, VLSIC 2013 - Digest of Technical Papers. 2013. p. C240-C241. 6578678. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).

A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application

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