A technology path for scaling embedded FeRAM to 28nm with 2T1C structure

Jae Hur, Yuan Chun Luo, Zheng Wang, Wonbo Shim, Asif Islam Khan, Shimeng Yu

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

7 Scopus citations

Abstract

Hf0.5Zr0.5O2 (HZO) ferroelectric random access memory (FeRAM) has been demonstrated in 130nm node with 1T1C structure. To scale FeRAM to 28nm or beyond, a high-aspect ratio embedded DRAM-like 3D cylinder capacitor is expected to ensure sufficient cell capacitance and sense margin. In this work, we investigate an alternative approach with 2T1C structure that takes advantages of a back-end-of-line (BEOL) oxide channel writing transistor, a small planar ferroelectric capacitor, and a silicon logic reading transistor. Firstly, the proof-of-concept of 2T1C bit cell was experimentally demonstrated. Then, the scalability towards 28nm was simulated with array-level parasitics. Thanks to the transconductance reading out mechanism, a 784 nm2 ferroelectric capacitor in 2T1C could significantly reduce energy consumption 6.5-11× compared to the traditional 1T1C FeRAM with similar cell area at 28nm.

Original languageEnglish
Title of host publication2021 IEEE International Memory Workshop, IMW 2021 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728185170
DOIs
StatePublished - May 2021
Event2021 IEEE International Memory Workshop, IMW 2021 - Dresden, Germany
Duration: 16 May 202119 May 2021

Publication series

Name2021 IEEE International Memory Workshop, IMW 2021 - Proceedings

Conference

Conference2021 IEEE International Memory Workshop, IMW 2021
Country/TerritoryGermany
CityDresden
Period16/05/2119/05/21

Keywords

  • BEOL
  • FeRAM
  • ferroelectrics
  • HZO
  • NVM

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