A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout

Ji Wook Kwon; Dong Hwan Jin; Hyeon June Kim; Sun Il Hwang; Min Chul Shin; Jong Ho Kang; Seung Tak Ryu

doi:10.1109/CICC.2014.6946034

A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout

Ji Wook Kwon
, Dong Hwan Jin
, Hyeon June Kim
, Sun Il Hwang
, Min Chul Shin
, Jong Ho Kang
, Seung Tak Ryu

Dept. of Semiconductor Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

6 Scopus citations

Abstract

A compact two-step 5b logarithmic ADC is designed for the readout application of multi-level cell phase-change memory (PCM). A bleeding-current-assisted regulated-cascode stage accurately converts the wide-dynamic range resistance of a PCM cell into a current. The designed ADC is composed of a logarithmic 2b current-mode flash ADC as a coarse ADC and a logarithmic 3b time-to-digital converter as a fine ADC with redundancy, resulting in compact size and low power consumption. The minimum step-size of the ADC is 0.1% of the full scale and the conversion time is 100 ns. The chip was fabricated in a 65 nm CMOS and the width of a single channel ADC is 15 μm. Single-channel ADC consumes 108 μW at 10 MS/s conversion rate under a 1.2 V supply.

Original language	English
Title of host publication	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781479932863
DOIs	https://doi.org/10.1109/CICC.2014.6946034
State	Published - 4 Nov 2014
Event	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 - San Jose, United States Duration: 15 Sep 2014 → 17 Sep 2014

Publication series

Name	Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014

Conference

Conference	36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014
Country/Territory	United States
City	San Jose
Period	15/09/14 → 17/09/14

Keywords

logarithmic ADC
multi-level cell
phase-change memory
resistance-to-current converter (R2I)

Access to Document

10.1109/CICC.2014.6946034

Cite this

Kwon, J. W., Jin, D. H., Kim, H. J., Hwang, S. I., Shin, M. C., Kang, J. H., & Ryu, S. T. (2014). A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014 Article 6946034 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/CICC.2014.6946034

Kwon, Ji Wook ; Jin, Dong Hwan ; Kim, Hyeon June et al. / A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

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title = "A two-step 5b logarithmic ADC with minimum step-size of 0.1\% full-scale for MLC phase-change memory readout",

abstract = "A compact two-step 5b logarithmic ADC is designed for the readout application of multi-level cell phase-change memory (PCM). A bleeding-current-assisted regulated-cascode stage accurately converts the wide-dynamic range resistance of a PCM cell into a current. The designed ADC is composed of a logarithmic 2b current-mode flash ADC as a coarse ADC and a logarithmic 3b time-to-digital converter as a fine ADC with redundancy, resulting in compact size and low power consumption. The minimum step-size of the ADC is 0.1\% of the full scale and the conversion time is 100 ns. The chip was fabricated in a 65 nm CMOS and the width of a single channel ADC is 15 μm. Single-channel ADC consumes 108 μW at 10 MS/s conversion rate under a 1.2 V supply.",

keywords = "logarithmic ADC, multi-level cell, phase-change memory, resistance-to-current converter (R2I)",

author = "Kwon, \{Ji Wook\} and Jin, \{Dong Hwan\} and Kim, \{Hyeon June\} and Hwang, \{Sun Il\} and Shin, \{Min Chul\} and Kang, \{Jong Ho\} and Ryu, \{Seung Tak\}",

note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014 ; Conference date: 15-09-2014 Through 17-09-2014",

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doi = "10.1109/CICC.2014.6946034",

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Kwon, JW, Jin, DH, Kim, HJ, Hwang, SI, Shin, MC, Kang, JH & Ryu, ST 2014, A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. in Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014., 6946034, Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014, Institute of Electrical and Electronics Engineers Inc., 36th Annual Custom Integrated Circuits Conference - The Showcase for Integrated Circuit Design in the Heart of Silicon Valley, CICC 2014, San Jose, United States, 15/09/14. https://doi.org/10.1109/CICC.2014.6946034

A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. / Kwon, Ji Wook; Jin, Dong Hwan; Kim, Hyeon June et al.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc., 2014. 6946034 (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Kwon, Ji Wook

AU - Jin, Dong Hwan

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AU - Hwang, Sun Il

AU - Shin, Min Chul

AU - Kang, Jong Ho

AU - Ryu, Seung Tak

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N2 - A compact two-step 5b logarithmic ADC is designed for the readout application of multi-level cell phase-change memory (PCM). A bleeding-current-assisted regulated-cascode stage accurately converts the wide-dynamic range resistance of a PCM cell into a current. The designed ADC is composed of a logarithmic 2b current-mode flash ADC as a coarse ADC and a logarithmic 3b time-to-digital converter as a fine ADC with redundancy, resulting in compact size and low power consumption. The minimum step-size of the ADC is 0.1% of the full scale and the conversion time is 100 ns. The chip was fabricated in a 65 nm CMOS and the width of a single channel ADC is 15 μm. Single-channel ADC consumes 108 μW at 10 MS/s conversion rate under a 1.2 V supply.

AB - A compact two-step 5b logarithmic ADC is designed for the readout application of multi-level cell phase-change memory (PCM). A bleeding-current-assisted regulated-cascode stage accurately converts the wide-dynamic range resistance of a PCM cell into a current. The designed ADC is composed of a logarithmic 2b current-mode flash ADC as a coarse ADC and a logarithmic 3b time-to-digital converter as a fine ADC with redundancy, resulting in compact size and low power consumption. The minimum step-size of the ADC is 0.1% of the full scale and the conversion time is 100 ns. The chip was fabricated in a 65 nm CMOS and the width of a single channel ADC is 15 μm. Single-channel ADC consumes 108 μW at 10 MS/s conversion rate under a 1.2 V supply.

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KW - multi-level cell

KW - phase-change memory

KW - resistance-to-current converter (R2I)

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Kwon JW, Jin DH, Kim HJ, Hwang SI, Shin MC, Kang JH et al. A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout. In Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014. Institute of Electrical and Electronics Engineers Inc. 2014. 6946034. (Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, CICC 2014). doi: 10.1109/CICC.2014.6946034

A two-step 5b logarithmic ADC with minimum step-size of 0.1% full-scale for MLC phase-change memory readout

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Keywords

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