A unified graphics and vision processor with a 0.89 μw/fps pose estimation engine for augmented reality

Jae Sung Yoon; Jeong Hyun Kim; Hyo Eun Kim; Won Young Lee; Seok Hoon Kim; Kyusik Chung; Jun Seok Park; Lee Sup Kim

doi:10.1109/TVLSI.2012.2186157

A unified graphics and vision processor with a 0.89 μw/fps pose estimation engine for augmented reality

Jae Sung Yoon, Jeong Hyun Kim, Hyo Eun Kim, Won Young Lee, Seok Hoon Kim, Kyusik Chung, Jun Seok Park, Lee Sup Kim

Media IT Engineering Program

Korea Advanced Institute of Science and Technology

Research output: Contribution to journal › Article › peer-review

22 Scopus citations

Abstract

A unified vision and graphics processor with three layers is shown to provide a fast pipeline for augmented reality. In the image-level layer, a 153.6 GOPS massively parallel processing unit with eight SIMD processors, each containing 128 processing elements, performs highly data-parallel operations. In the sub-image layer, a rasterizer and a pixel arranger respectively generate and reduce data-level parallelism. In the descriptor-level layer, a pose estimation engine executes sequential programs. Our processor can provide images for augmented reality at 100 fps, for a power consumption of 413 mW. This is 39% faster than a comparable smartphone implementation. Our chip is fabricated in a 0.18 μm CMOS process and contains 0.95 M gates.

Original language	English
Article number	6156811
Pages (from-to)	206-216
Number of pages	11
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	21
Issue number	2
DOIs	https://doi.org/10.1109/TVLSI.2012.2186157
State	Published - 2013

Keywords

3-D graphics
augmented reality (AR)
pose estimation
vision processor

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10.1109/TVLSI.2012.2186157

Cite this

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abstract = "A unified vision and graphics processor with three layers is shown to provide a fast pipeline for augmented reality. In the image-level layer, a 153.6 GOPS massively parallel processing unit with eight SIMD processors, each containing 128 processing elements, performs highly data-parallel operations. In the sub-image layer, a rasterizer and a pixel arranger respectively generate and reduce data-level parallelism. In the descriptor-level layer, a pose estimation engine executes sequential programs. Our processor can provide images for augmented reality at 100 fps, for a power consumption of 413 mW. This is 39\% faster than a comparable smartphone implementation. Our chip is fabricated in a 0.18 μm CMOS process and contains 0.95 M gates.",

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AU - Yoon, Jae Sung

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AU - Lee, Won Young

AU - Kim, Seok Hoon

AU - Chung, Kyusik

AU - Park, Jun Seok

AU - Kim, Lee Sup

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AB - A unified vision and graphics processor with three layers is shown to provide a fast pipeline for augmented reality. In the image-level layer, a 153.6 GOPS massively parallel processing unit with eight SIMD processors, each containing 128 processing elements, performs highly data-parallel operations. In the sub-image layer, a rasterizer and a pixel arranger respectively generate and reduce data-level parallelism. In the descriptor-level layer, a pose estimation engine executes sequential programs. Our processor can provide images for augmented reality at 100 fps, for a power consumption of 413 mW. This is 39% faster than a comparable smartphone implementation. Our chip is fabricated in a 0.18 μm CMOS process and contains 0.95 M gates.

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A unified graphics and vision processor with a 0.89 μw/fps pose estimation engine for augmented reality

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Keywords

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