Abstract
A back-end-of-the-line (BEOL) compatible wafer-level three-dimensional (3D) IC technology platform using dielectric glue bonding, three-step wafer thinning and copper dual-inlaid inter-wafer interconnects is described. Electrical results before and after bonding and thinning processes are summarized for passive interconnect structures with copper and both oxide and porous low-k interlevel dielectrics (ILDs) and are presented for the first time for 130nm technology node CMOS SOI ICs with four-level copper/low-k interconnects. Results on ring oscillator delay, n-channel and p-channel threshold voltage and gate leakage indicate that changes in electrical parameters are less than one-third of the 10%-90% distribution spread in original parameter values. Via-chain test structure results indicating the viability of such a 3D IC technology platform are summarized, and new results indicating compatibility with conventional die packaging techniques are presented.
| Original language | English |
|---|---|
| Pages (from-to) | 19-26 |
| Number of pages | 8 |
| Journal | Advanced Metallization Conference (AMC) |
| State | Published - 2003 |
| Event | Advanced Metallization Conference 2003, AMC 2003 - Montreal, Que., Canada Duration: 21 Oct 2003 → 23 Oct 2003 |