A wafer-level 3D IC technology platform

R. J. Gutmann; J. Q. Lu; S. Pozder; Y. Kwon; D. Menke; A. Jindal; M. Celik; M. Rasco; J. J. McMahon; K. Yu; T. S. Cale

A wafer-level 3D IC technology platform

R. J. Gutmann
, J. Q. Lu
, S. Pozder
, Y. Kwon
, D. Menke
, A. Jindal
, M. Celik
, M. Rasco
, J. J. McMahon
, K. Yu
, T. S. Cale

Dept. of Chemical and Biomolecular Engineering

Research output: Contribution to journal › Conference article › peer-review

41 Scopus citations

Abstract

A back-end-of-the-line (BEOL) compatible wafer-level three-dimensional (3D) IC technology platform using dielectric glue bonding, three-step wafer thinning and copper dual-inlaid inter-wafer interconnects is described. Electrical results before and after bonding and thinning processes are summarized for passive interconnect structures with copper and both oxide and porous low-k interlevel dielectrics (ILDs) and are presented for the first time for 130nm technology node CMOS SOI ICs with four-level copper/low-k interconnects. Results on ring oscillator delay, n-channel and p-channel threshold voltage and gate leakage indicate that changes in electrical parameters are less than one-third of the 10%-90% distribution spread in original parameter values. Via-chain test structure results indicating the viability of such a 3D IC technology platform are summarized, and new results indicating compatibility with conventional die packaging techniques are presented.

Original language	English
Pages (from-to)	19-26
Number of pages	8
Journal	Advanced Metallization Conference (AMC)
State	Published - 2003
Event	Advanced Metallization Conference 2003, AMC 2003 - Montreal, Que., Canada Duration: 21 Oct 2003 → 23 Oct 2003

Cite this

@article{1244ca4ce2254bb5b125c8023ec2de54,

title = "A wafer-level 3D IC technology platform",

abstract = "A back-end-of-the-line (BEOL) compatible wafer-level three-dimensional (3D) IC technology platform using dielectric glue bonding, three-step wafer thinning and copper dual-inlaid inter-wafer interconnects is described. Electrical results before and after bonding and thinning processes are summarized for passive interconnect structures with copper and both oxide and porous low-k interlevel dielectrics (ILDs) and are presented for the first time for 130nm technology node CMOS SOI ICs with four-level copper/low-k interconnects. Results on ring oscillator delay, n-channel and p-channel threshold voltage and gate leakage indicate that changes in electrical parameters are less than one-third of the 10\%-90\% distribution spread in original parameter values. Via-chain test structure results indicating the viability of such a 3D IC technology platform are summarized, and new results indicating compatibility with conventional die packaging techniques are presented.",

author = "Gutmann, \{R. J.\} and Lu, \{J. Q.\} and S. Pozder and Y. Kwon and D. Menke and A. Jindal and M. Celik and M. Rasco and McMahon, \{J. J.\} and K. Yu and Cale, \{T. S.\}",

year = "2003",

language = "English",

pages = "19--26",

journal = "Advanced Metallization Conference (AMC)",

issn = "1540-1766",

note = "Advanced Metallization Conference 2003, AMC 2003 ; Conference date: 21-10-2003 Through 23-10-2003",

}

TY - JOUR

T1 - A wafer-level 3D IC technology platform

AU - Gutmann, R. J.

AU - Lu, J. Q.

AU - Pozder, S.

AU - Kwon, Y.

AU - Menke, D.

AU - Jindal, A.

AU - Celik, M.

AU - Rasco, M.

AU - McMahon, J. J.

AU - Yu, K.

AU - Cale, T. S.

PY - 2003

Y1 - 2003

N2 - A back-end-of-the-line (BEOL) compatible wafer-level three-dimensional (3D) IC technology platform using dielectric glue bonding, three-step wafer thinning and copper dual-inlaid inter-wafer interconnects is described. Electrical results before and after bonding and thinning processes are summarized for passive interconnect structures with copper and both oxide and porous low-k interlevel dielectrics (ILDs) and are presented for the first time for 130nm technology node CMOS SOI ICs with four-level copper/low-k interconnects. Results on ring oscillator delay, n-channel and p-channel threshold voltage and gate leakage indicate that changes in electrical parameters are less than one-third of the 10%-90% distribution spread in original parameter values. Via-chain test structure results indicating the viability of such a 3D IC technology platform are summarized, and new results indicating compatibility with conventional die packaging techniques are presented.

AB - A back-end-of-the-line (BEOL) compatible wafer-level three-dimensional (3D) IC technology platform using dielectric glue bonding, three-step wafer thinning and copper dual-inlaid inter-wafer interconnects is described. Electrical results before and after bonding and thinning processes are summarized for passive interconnect structures with copper and both oxide and porous low-k interlevel dielectrics (ILDs) and are presented for the first time for 130nm technology node CMOS SOI ICs with four-level copper/low-k interconnects. Results on ring oscillator delay, n-channel and p-channel threshold voltage and gate leakage indicate that changes in electrical parameters are less than one-third of the 10%-90% distribution spread in original parameter values. Via-chain test structure results indicating the viability of such a 3D IC technology platform are summarized, and new results indicating compatibility with conventional die packaging techniques are presented.

UR - https://www.scopus.com/pages/publications/23844497416

M3 - Conference article

AN - SCOPUS:23844497416

SN - 1540-1766

SP - 19

EP - 26

JO - Advanced Metallization Conference (AMC)

JF - Advanced Metallization Conference (AMC)

T2 - Advanced Metallization Conference 2003, AMC 2003

Y2 - 21 October 2003 through 23 October 2003

ER -

A wafer-level 3D IC technology platform

Abstract

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