A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

J. Q. Lu; Y. Kwon; G. Rajagopalan; M. Gupta; J. McMahon; K. W. Lee; R. P. Kraft; J. F. McDonald; T. S. Cale; R. J. Gutmann; B. Xu; E. Eisenbraun; J. Castracane; A. Kaloyeros

doi:10.1109/IITC.2002.1014893

A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

J. Q. Lu
, Y. Kwon
, G. Rajagopalan
, M. Gupta
, J. McMahon
, K. W. Lee
, R. P. Kraft
, J. F. McDonald
, T. S. Cale
, R. J. Gutmann
, B. Xu
, E. Eisenbraun
, J. Castracane
, A. Kaloyeros

Dept. of Chemical and Biomolecular Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

33 Scopus citations

Abstract

A viable approach for a monolithic wafer-scale three-dimensional (3D) IC technology platform is presented, focusing on wafer bonding, wafer thinning and inter-wafer damascene-patterned interconnects. Principal results include successful wafer alignment, wafer bonding with both BCB and Flare, post bonding wafer thinning using grinding and polishing to 35-50 μm, and via etch through the required material stack.

Original language	English
Title of host publication	Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	78-80
Number of pages	3
ISBN (Electronic)	0780372166, 9780780372160
DOIs	https://doi.org/10.1109/IITC.2002.1014893
State	Published - 2002
Event	IEEE International Interconnect Technology Conference, IITC 2002 - Burlingame, United States Duration: 3 Jun 2002 → 5 Jun 2002

Publication series

Name	Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

Conference

Conference	IEEE International Interconnect Technology Conference, IITC 2002
Country/Territory	United States
City	Burlingame
Period	3/06/02 → 5/06/02

Access to Document

10.1109/IITC.2002.1014893

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Lu, J. Q., Kwon, Y., Rajagopalan, G., Gupta, M., McMahon, J., Lee, K. W., Kraft, R. P., McDonald, J. F., Cale, T. S., Gutmann, R. J., Xu, B., Eisenbraun, E., Castracane, J., & Kaloyeros, A. (2002). A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects. In Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002 (pp. 78-80). Article 1014893 (Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IITC.2002.1014893

Lu, J. Q. ; Kwon, Y. ; Rajagopalan, G. et al. / A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects. Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 78-80 (Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002).

@inproceedings{53bd158c7a764705af2e190928cfb9ec,

title = "A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects",

abstract = "A viable approach for a monolithic wafer-scale three-dimensional (3D) IC technology platform is presented, focusing on wafer bonding, wafer thinning and inter-wafer damascene-patterned interconnects. Principal results include successful wafer alignment, wafer bonding with both BCB and Flare, post bonding wafer thinning using grinding and polishing to 35-50 μm, and via etch through the required material stack.",

author = "Lu, \{J. Q.\} and Y. Kwon and G. Rajagopalan and M. Gupta and J. McMahon and Lee, \{K. W.\} and Kraft, \{R. P.\} and McDonald, \{J. F.\} and Cale, \{T. S.\} and Gutmann, \{R. J.\} and B. Xu and E. Eisenbraun and J. Castracane and A. Kaloyeros",

note = "Publisher Copyright: {\textcopyright} 2002 IEEE.; IEEE International Interconnect Technology Conference, IITC 2002 ; Conference date: 03-06-2002 Through 05-06-2002",

year = "2002",

doi = "10.1109/IITC.2002.1014893",

language = "English",

series = "Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "78--80",

booktitle = "Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002",

}

Lu, JQ, Kwon, Y, Rajagopalan, G, Gupta, M, McMahon, J, Lee, KW, Kraft, RP, McDonald, JF, Cale, TS, Gutmann, RJ, Xu, B, Eisenbraun, E, Castracane, J & Kaloyeros, A 2002, A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects. in Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002., 1014893, Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002, Institute of Electrical and Electronics Engineers Inc., pp. 78-80, IEEE International Interconnect Technology Conference, IITC 2002, Burlingame, United States, 3/06/02. https://doi.org/10.1109/IITC.2002.1014893

A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects. / Lu, J. Q.; Kwon, Y.; Rajagopalan, G. et al.
Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002. Institute of Electrical and Electronics Engineers Inc., 2002. p. 78-80 1014893 (Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

AU - Lu, J. Q.

AU - Kwon, Y.

AU - Rajagopalan, G.

AU - Gupta, M.

AU - McMahon, J.

AU - Lee, K. W.

AU - Kraft, R. P.

AU - McDonald, J. F.

AU - Cale, T. S.

AU - Gutmann, R. J.

AU - Xu, B.

AU - Eisenbraun, E.

AU - Castracane, J.

AU - Kaloyeros, A.

PY - 2002

Y1 - 2002

N2 - A viable approach for a monolithic wafer-scale three-dimensional (3D) IC technology platform is presented, focusing on wafer bonding, wafer thinning and inter-wafer damascene-patterned interconnects. Principal results include successful wafer alignment, wafer bonding with both BCB and Flare, post bonding wafer thinning using grinding and polishing to 35-50 μm, and via etch through the required material stack.

AB - A viable approach for a monolithic wafer-scale three-dimensional (3D) IC technology platform is presented, focusing on wafer bonding, wafer thinning and inter-wafer damascene-patterned interconnects. Principal results include successful wafer alignment, wafer bonding with both BCB and Flare, post bonding wafer thinning using grinding and polishing to 35-50 μm, and via etch through the required material stack.

UR - https://www.scopus.com/pages/publications/84961736622

U2 - 10.1109/IITC.2002.1014893

DO - 10.1109/IITC.2002.1014893

M3 - Conference contribution

AN - SCOPUS:84961736622

T3 - Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

SP - 78

EP - 80

BT - Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - IEEE International Interconnect Technology Conference, IITC 2002

Y2 - 3 June 2002 through 5 June 2002

ER -

Lu JQ, Kwon Y, Rajagopalan G, Gupta M, McMahon J, Lee KW et al. A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects. In Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 78-80. 1014893. (Proceedings of the IEEE 2002 International Interconnect Technology Conference, IITC 2002). doi: 10.1109/IITC.2002.1014893

A wafer-scale 3D IC technology platform using dielectric bonding glues and copper damascene patterned inter-wafer interconnects

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