@inproceedings{6930268f44c64104a0fbe634daa809a3,
title = "A Wide-Range Reference-Less Digital Clock and Data Recovery for Harmonic-Lock-Free Frequency Acquisition",
abstract = "This paper presents a digital clock and data recovery (CDR) designed for a faster approach to its steady-state and prevention of harmonic locking. By adopting a two-stage frequency detection system, the proposed CDR ensures a rapid and robust harmonic-lock-free frequency acquisition. The circuit is implemented and fabricated in a 28 nm CMOS process using a 1.0 V supply. The active area occupies 0.12 mm2. It covers from 1.62 to 8.1 Gb/s, making it adaptable to embedded DisplayPort (eDP) interfaces. The prototype achieves the rms jitter and the peak-to-peak jitter is 5.54 psrms and 27.53 pspp at 8.1 Gb/s, respectively. Its lock time is reduced within 2 μs for +170\% frequency error.",
keywords = "all-digital, antiharmonic-lock, Clock and data recovery, fast locking, reference-less",
author = "Lee, \{Hyun Bin\} and Yoon Heo and Lee, \{Won Young\}",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 IEEE International Symposium on Circuits and Systems, ISCAS 2024 ; Conference date: 19-05-2024 Through 22-05-2024",
year = "2024",
doi = "10.1109/ISCAS58744.2024.10557972",
language = "English",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "ISCAS 2024 - IEEE International Symposium on Circuits and Systems",
}