An adaptive equalizer with the capacitance multiplication for DisplayPort main link in 0.18-μm CMOS

Won Young Lee; Lee Sup Kim

doi:10.1109/TVLSI.2011.2130546

An adaptive equalizer with the capacitance multiplication for DisplayPort main link in 0.18-μm CMOS

Won Young Lee, Lee Sup Kim

Media IT Engineering Program

Korea Advanced Institute of Science and Technology

Research output: Contribution to journal › Article › peer-review

8 Scopus citations

Abstract

An adaptive equalizer with the capacitance multiplication for DisplayPort main link has been proposed. The proposed equalizing filter is based on Miller's theorem and composed of metal-insulator-metal capacitors and a sub-amplifier. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication. The equalizer satisfies the specification of DisplayPort version 1.1a. The measured eye widths of 2.7 Gb/s data are 0.6 and 0.5 UI for 5 and 8 m cables, respectively. The core area is 286 × 380 μm ² and power consumption is 22.3 mW at 2.7 Gb/s at 1.8 V.

Original language	English
Article number	5746557
Pages (from-to)	964-968
Number of pages	5
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	20
Issue number	5
DOIs	https://doi.org/10.1109/TVLSI.2011.2130546
State	Published - May 2012

Keywords

Adaptive equalizer
capacitance multiplication
DisplayPort

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10.1109/TVLSI.2011.2130546

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abstract = "An adaptive equalizer with the capacitance multiplication for DisplayPort main link has been proposed. The proposed equalizing filter is based on Miller's theorem and composed of metal-insulator-metal capacitors and a sub-amplifier. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication. The equalizer satisfies the specification of DisplayPort version 1.1a. The measured eye widths of 2.7 Gb/s data are 0.6 and 0.5 UI for 5 and 8 m cables, respectively. The core area is 286 × 380 μm 2 and power consumption is 22.3 mW at 2.7 Gb/s at 1.8 V.",

keywords = "Adaptive equalizer, capacitance multiplication, DisplayPort",

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AB - An adaptive equalizer with the capacitance multiplication for DisplayPort main link has been proposed. The proposed equalizing filter is based on Miller's theorem and composed of metal-insulator-metal capacitors and a sub-amplifier. The active source degeneration capacitor achieves low cost and area saving with the capacitance multiplication. The equalizer satisfies the specification of DisplayPort version 1.1a. The measured eye widths of 2.7 Gb/s data are 0.6 and 0.5 UI for 5 and 8 m cables, respectively. The core area is 286 × 380 μm 2 and power consumption is 22.3 mW at 2.7 Gb/s at 1.8 V.

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An adaptive equalizer with the capacitance multiplication for DisplayPort main link in 0.18-μm CMOS

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Keywords

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