An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate Clock and Data Recovery

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Abstract

This paper presents a frequency detector (FD) for a continuous-rate clock and data recovery (CDR). The study analyzes the harmonic locking issue occurring in wide-range CDR and introduces the FD to prevent harmonic lock. It achieves anti-harmonic lock and fast lock time using coarse and fine frequency tuning. The conventional single-loop CDR incorporating the proposed FD is implemented and simulated in 65-nm CMOS technology. The capture range is 4-to-9 Gb/s and the locking time is shorter than 2 μs for the maximum frequency offset of 7 GHz.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2023, ISOCC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages111-112
Number of pages2
ISBN (Electronic)9798350327038
DOIs
StatePublished - 2023
Event20th International SoC Design Conference, ISOCC 2023 - Jeju, Korea, Republic of
Duration: 25 Oct 202328 Oct 2023

Publication series

NameProceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Conference20th International SoC Design Conference, ISOCC 2023
Country/TerritoryKorea, Republic of
CityJeju
Period25/10/2328/10/23

Keywords

  • anti-harmonic-lock
  • clock and data recovery
  • continuous-rate
  • digital
  • reference-less

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