An approximate DRAM with efficient refresh schemes for low power deep learning applications

Duy Thanh Nguyen, Hyuk Jae Lee, Hyun Kim, Ik Joon Chang

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

4 Scopus citations

Abstract

To avoid the accuracy drop caused by slowing down the refresh rate of a DRAM, the proposed approximate DRAM flexibly controls the refresh operation for different bits of data. Data are reorganized and mapped to different DRAM devices according to their bit significance. More critical bits are stored in more frequently refreshed devices while non-critical bits are stored in less frequently refreshed devices. Compared to the conventional DRAM, the proposed approximate DRAM requires only a separation of the chip select signal for each device in a DRAM rank and a minor change in the memory controller. Simulation results show that the refresh power consumption is reduced by 66.5 % with a negligible accuracy drop in computation for state-of-the-art deep networks.

Original languageEnglish
Title of host publication2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781728162898
DOIs
StatePublished - Jan 2020
Event2020 International Conference on Electronics, Information, and Communication, ICEIC 2020 - Barcelona, Spain
Duration: 19 Jan 202022 Jan 2020

Publication series

Name2020 International Conference on Electronics, Information, and Communication, ICEIC 2020

Conference

Conference2020 International Conference on Electronics, Information, and Communication, ICEIC 2020
Country/TerritorySpain
CityBarcelona
Period19/01/2022/01/20

Keywords

  • Approximate computing
  • Approximate DRAM
  • Deep learning
  • Fine-grained refresh
  • Low power DRAM

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