Abstract
This brief proposes a novel method to determine the best combination of operation conditions for multiple power-scaling schemes. The power saving and rate-distortion performances of individual schemes are simulated, and then, the combined effects are modeled to obtain the best operation combination. The optimized combinations are defined as a power-level table. The proposed power-aware design is tested with four popular power-saving schemes and simulations show that a power saving of ∼ 25 % is achieved at the sacrifice of < 0.172dB Bjontegaard Delta peak signal-to-noise ratio degradation.
| Original language | English |
|---|---|
| Article number | 6967803 |
| Pages (from-to) | 2685-2689 |
| Number of pages | 5 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 23 |
| Issue number | 11 |
| DOIs | |
| State | Published - Nov 2015 |
Keywords
- H.264/AVC
- power reduction
- power-aware design
- power-scaling scheme
- Real-time application