An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces

Seul Ki Han, Won Young Lee

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

Abstract

This paper presents a duobinary transceiver designed for low-power and high-speed serial interfaces. The proposed circuit can simply implement by using novel architecture of duobinary precoder and decoder. The transceiver was designed in 28nm CMOS technology and verified through the post-layout simulation. And the measured energy efficiency is 1.12pJ/bit at 21Gb/s.

Original languageEnglish
Title of host publicationISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9798350356830
DOIs
StatePublished - 2025
Event2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom
Duration: 25 May 202528 May 2025

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)0271-4310

Conference

Conference2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Country/TerritoryUnited Kingdom
CityLondon
Period25/05/2528/05/25

Keywords

  • dc offset
  • Duobinary
  • precoder
  • timing constraint

Fingerprint

Dive into the research topics of 'An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces'. Together they form a unique fingerprint.

Cite this