An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces

Seul Ki Han; Won Young Lee

doi:10.1109/ISCAS56072.2025.11044001

An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces

Seul Ki Han
, Won Young Lee

Media IT Engineering Program

Seoul National University of Science and Technology (SNUST)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

Abstract

This paper presents a duobinary transceiver designed for low-power and high-speed serial interfaces. The proposed circuit can simply implement by using novel architecture of duobinary precoder and decoder. The transceiver was designed in 28nm CMOS technology and verified through the post-layout simulation. And the measured energy efficiency is 1.12pJ/bit at 21Gb/s.

Original language	English
Title of host publication	ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9798350356830
DOIs	https://doi.org/10.1109/ISCAS56072.2025.11044001
State	Published - 2025
Event	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 - London, United Kingdom Duration: 25 May 2025 → 28 May 2025

Publication series

Name	Proceedings - IEEE International Symposium on Circuits and Systems
ISSN (Print)	0271-4310

Conference

Conference	2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025
Country/Territory	United Kingdom
City	London
Period	25/05/25 → 28/05/25

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

dc offset
Duobinary
precoder
timing constraint

Access to Document

10.1109/ISCAS56072.2025.11044001

Cite this

Han, S. K., & Lee, W. Y. (2025). An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces. In ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings (Proceedings - IEEE International Symposium on Circuits and Systems). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCAS56072.2025.11044001

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title = "An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces",

abstract = "This paper presents a duobinary transceiver designed for low-power and high-speed serial interfaces. The proposed circuit can simply implement by using novel architecture of duobinary precoder and decoder. The transceiver was designed in 28nm CMOS technology and verified through the post-layout simulation. And the measured energy efficiency is 1.12pJ/bit at 21Gb/s.",

keywords = "dc offset, Duobinary, precoder, timing constraint",

author = "Han, \{Seul Ki\} and Lee, \{Won Young\}",

note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025 ; Conference date: 25-05-2025 Through 28-05-2025",

year = "2025",

doi = "10.1109/ISCAS56072.2025.11044001",

language = "English",

series = "Proceedings - IEEE International Symposium on Circuits and Systems",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings",

}

Han, SK & Lee, WY 2025, An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces. in ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Proceedings - IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers Inc., 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025, London, United Kingdom, 25/05/25. https://doi.org/10.1109/ISCAS56072.2025.11044001

An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces. / Han, Seul Ki; Lee, Won Young.
ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings. Institute of Electrical and Electronics Engineers Inc., 2025. (Proceedings - IEEE International Symposium on Circuits and Systems).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces

AU - Han, Seul Ki

AU - Lee, Won Young

PY - 2025

Y1 - 2025

N2 - This paper presents a duobinary transceiver designed for low-power and high-speed serial interfaces. The proposed circuit can simply implement by using novel architecture of duobinary precoder and decoder. The transceiver was designed in 28nm CMOS technology and verified through the post-layout simulation. And the measured energy efficiency is 1.12pJ/bit at 21Gb/s.

AB - This paper presents a duobinary transceiver designed for low-power and high-speed serial interfaces. The proposed circuit can simply implement by using novel architecture of duobinary precoder and decoder. The transceiver was designed in 28nm CMOS technology and verified through the post-layout simulation. And the measured energy efficiency is 1.12pJ/bit at 21Gb/s.

KW - dc offset

KW - Duobinary

KW - precoder

KW - timing constraint

UR - https://www.scopus.com/pages/publications/105010646236

U2 - 10.1109/ISCAS56072.2025.11044001

DO - 10.1109/ISCAS56072.2025.11044001

M3 - Conference contribution

AN - SCOPUS:105010646236

T3 - Proceedings - IEEE International Symposium on Circuits and Systems

BT - ISCAS 2025 - IEEE International Symposium on Circuits and Systems, Proceedings

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2025 IEEE International Symposium on Circuits and Systems, ISCAS 2025

Y2 - 25 May 2025 through 28 May 2025

ER -

An Energy-Efficient 21Gb/s Duobinary Transceiver for High-Speed Serial Interfaces

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

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