An integrated wafer-scale packaging process for MEMS

Thomas W. Kenny; Rob N. Candler; Huimou J. Li; Woo Tae Park; Junghwa Cho; Holden Li; Aaron Partridge; Gary Yama; Marcus Lutz

doi:10.1115/IMECE2002-39270

An integrated wafer-scale packaging process for MEMS

Thomas W. Kenny, Rob N. Candler, Huimou J. Li, Woo Tae Park, Junghwa Cho, Holden Li, Aaron Partridge, Gary Yama, Marcus Lutz

Dept. of Mechanical & Automotive Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

3 Scopus citations

Abstract

Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

Original language	English
Title of host publication	Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology
Publisher	American Society of Mechanical Engineers (ASME)
Pages	51-54
Number of pages	4
ISBN (Print)	0791836487, 9780791836484
DOIs	https://doi.org/10.1115/IMECE2002-39270
State	Published - 2002

Publication series

Name	ASME International Mechanical Engineering Congress and Exposition, Proceedings

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10.1115/IMECE2002-39270

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Kenny, T. W., Candler, R. N., Li, H. J., Park, W. T., Cho, J., Li, H., Partridge, A., Yama, G., & Lutz, M. (2002). An integrated wafer-scale packaging process for MEMS. In Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology (pp. 51-54). (ASME International Mechanical Engineering Congress and Exposition, Proceedings). American Society of Mechanical Engineers (ASME). https://doi.org/10.1115/IMECE2002-39270

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abstract = "Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.",

author = "Kenny, \{Thomas W.\} and Candler, \{Rob N.\} and Li, \{Huimou J.\} and Park, \{Woo Tae\} and Junghwa Cho and Holden Li and Aaron Partridge and Gary Yama and Marcus Lutz",

year = "2002",

doi = "10.1115/IMECE2002-39270",

language = "English",

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series = "ASME International Mechanical Engineering Congress and Exposition, Proceedings",

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Kenny, TW, Candler, RN, Li, HJ, Park, WT, Cho, J, Li, H, Partridge, A, Yama, G & Lutz, M 2002, An integrated wafer-scale packaging process for MEMS. in Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology. ASME International Mechanical Engineering Congress and Exposition, Proceedings, American Society of Mechanical Engineers (ASME), pp. 51-54. https://doi.org/10.1115/IMECE2002-39270

An integrated wafer-scale packaging process for MEMS. / Kenny, Thomas W.; Candler, Rob N.; Li, Huimou J. et al.
Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology. American Society of Mechanical Engineers (ASME), 2002. p. 51-54 (ASME International Mechanical Engineering Congress and Exposition, Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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AU - Partridge, Aaron

AU - Yama, Gary

AU - Lutz, Marcus

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AB - Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

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BT - Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology

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Kenny TW, Candler RN, Li HJ, Park WT, Cho J, Li H et al. An integrated wafer-scale packaging process for MEMS. In Electronic and Photonic Packaging, Electrical Systems Design and Photonics, and Nanotechnology. American Society of Mechanical Engineers (ASME). 2002. p. 51-54. (ASME International Mechanical Engineering Congress and Exposition, Proceedings). doi: 10.1115/IMECE2002-39270

An integrated wafer-scale packaging process for MEMS

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