An integrated wafer-scale packaging process for MEMS

Thomas W. Kenny; Rob N. Candler; Huimou J. Li; Woo Tae Park; Junghwa Cho; Holden Li; Aaron Partridge; Gary Yama; Marcus Lutz

doi:10.1115/IMECE2002-39270

An integrated wafer-scale packaging process for MEMS

Thomas W. Kenny
, Rob N. Candler
, Huimou J. Li
, Woo Tae Park
, Junghwa Cho
, Holden Li
, Aaron Partridge
, Gary Yama
, Marcus Lutz

Dept. of Mechanical & Automotive Engineering

Research output: Contribution to conference › Paper › peer-review

2 Scopus citations

Abstract

Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

Original language	English
Pages	51-54
Number of pages	4
DOIs	https://doi.org/10.1115/IMECE2002-39270
State	Published - 2002
Event	2002 ASME International Mechanical Engineering Congress and Exposition - New Orleans, LA, United States Duration: 17 Nov 2002 → 22 Nov 2002

Conference

Conference	2002 ASME International Mechanical Engineering Congress and Exposition
Country/Territory	United States
City	New Orleans, LA
Period	17/11/02 → 22/11/02

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1115/IMECE2002-39270

Cite this

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abstract = "Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.",

author = "Kenny, \{Thomas W.\} and Candler, \{Rob N.\} and Li, \{Huimou J.\} and Park, \{Woo Tae\} and Junghwa Cho and Holden Li and Aaron Partridge and Gary Yama and Marcus Lutz",

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doi = "10.1115/IMECE2002-39270",

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AU - Kenny, Thomas W.

AU - Candler, Rob N.

AU - Li, Huimou J.

AU - Park, Woo Tae

AU - Cho, Junghwa

AU - Li, Holden

AU - Partridge, Aaron

AU - Yama, Gary

AU - Lutz, Marcus

PY - 2002

Y1 - 2002

N2 - Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

AB - Packaging is well known to impose significant cost, performance and fabrication constraints on MEMS devices. We have developed a wafer-scale, integrated packaging process which enables a released MEMS device to be sealed within a thick layer of epi-polysilicon. This encapsulation may be tailored to withstand conventional dicing saws, pick/place chip handling equipment, and even high-pressure injection molding for plastic DIP packages. This architecture can be adapted to a variety of MEMS devices, and is compatible with integrated electronics. This paper will describe this packaging technique and discuss applications.

UR - https://www.scopus.com/pages/publications/0347602133

U2 - 10.1115/IMECE2002-39270

DO - 10.1115/IMECE2002-39270

M3 - Paper

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T2 - 2002 ASME International Mechanical Engineering Congress and Exposition

Y2 - 17 November 2002 through 22 November 2002

ER -

An integrated wafer-scale packaging process for MEMS

Abstract

Conference

UN SDGs

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