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An low complexity hardware implementation of MIMO detector with application to WLAN

  • Chanho Yoon
  • , Eunyoung Choi
  • , Jungbo Son
  • , Sok Kyu Lee
  • , Taehyun Jeon
  • Electronics and Telecommunications Research Institute

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

In this paper, we describe a FPGA implementation of MI MO detector for future wireless communication system with application to wireless LAN, targeted for upcoming 802.11n standard. The MIMO detector assumes 2 transmit and 3 receive antennas. In soft-output demapper, we apply channel state information which effectively weights reliability information to soft-decision output bits for enhanced link-level performance. The implementation complexity is significantly reduced by avoiding repeated pseudo-inverse calculation for interference cancellation of every received symbol vector. Furthermore, the overall processing time and fabrication area it takes can be significantly reduced by applying bit reduction technique.

Original languageEnglish
Title of host publication2006 IEEE 63rd Vehicular Technology Conference, VTC 2006-Spring - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2271-2275
Number of pages5
ISBN (Print)0780393929, 9780780393929
DOIs
StatePublished - 2006
Event63rd IEEE Vehicular Technology Conference, VTC 2006-Spring - Melbourne, Australia
Duration: 7 May 200610 Jul 2006

Publication series

NameIEEE Vehicular Technology Conference
Volume5
ISSN (Print)1550-2252

Conference

Conference63rd IEEE Vehicular Technology Conference, VTC 2006-Spring
Country/TerritoryAustralia
CityMelbourne
Period7/05/0610/07/06

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