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An Ultra-Compact and Wideband D-band Power Amplifier in 28nm CMOS with Area-Efficient Coupled Line-Based Matching Network

  • Hyo Ryeong Jeon
  • , Hokeun Lee
  • , Sang Gug Lee
  • , Kyung Sik Choi
  • Korea Advanced Institute of Science and Technology

Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

1 Scopus citations

Abstract

This paper presents an ultra-compact and wideband D-band power amplifier (PA) utilizing area-efficient coupled line (CPL)-based matching networks. The design overcomes the size limitation in the signal propagation direction by employing CPL-based matching networks and shunt capacitors, enhancing bandwidth while achieving a compact form factor. Implemented in a CMOS 28 nm process, the proposed 3-stage PA achieves a 3-dB bandwidth of 45.1 GHz with a peak gain of 12.2 dB, an OP 1 dB of 7.6 dBm, and a power-added efficiency (PAEmax) of 10.2%. With a core area of only 0.24 × 0.065 mm2, the PA achieves the highest OP1dB per unit area among D-band PAs based on CMOS bulk process, making it a leading candidate for 2-D scalable D-band beamforming transmitter arrays.

Original languageEnglish
Title of host publication2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025
EditorsJane Gu, Kenichi Okada
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages427-430
Number of pages4
ISBN (Electronic)9798331514112
DOIs
StatePublished - 2025
Event2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025 - San Francisco, United States
Duration: 15 Jun 202517 Jun 2025

Publication series

NameDigest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
ISSN (Print)1529-2517

Conference

Conference2025 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2025
Country/TerritoryUnited States
CitySan Francisco
Period15/06/2517/06/25

Keywords

  • D-band
  • bulk CMOS
  • compact wideband design
  • matching network
  • power amplifiers

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