Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine

Wonbo Shim; Hongwu Jiang; Xiaochen Peng; Shimeng Yu

doi:10.1145/3422575.3422779

Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine

Wonbo Shim
, Hongwu Jiang
, Xiaochen Peng
, Shimeng Yu

Dept. of Electrical and Information Engineering

Georgia Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

13 Scopus citations

Abstract

3D NAND Flash memory has been proposed as an attractive candidate of inference engine for deep neural network (DNN) owing to its ultra-high density and commercially matured fabrication technology. However, the peripheral circuits require to be modified to enable compute-in-memory (CIM) and the chip architectures need to be redesigned for an optimized dataflow. In this work, we present a design of 3D NAND-CIM accelerator based on the macro parameters from an industry-grade prototype chip. The DNN inference performance is evaluated using the DNN+ NeuroSim framework. To exploit the ultra-high density of 3D NAND Flash, both inputs and weights duplication strategies are introduced to improve the throughput. The benchmarking on a variety of VGG and ResNet networks was performed across technological candidates for CIM including SRAM, RRAM and 3D NAND. Compared to similar designs with SRAM or RRAM, the result shows that 3D NAND based CIM design can achieve not only 17-24% chip size but also 1.9-2.7 times more competitive energy efficiency for 8-bit precision inference.

Original language	English
Title of host publication	MEMSYS 2020 - Proceedings of the International Symposium on Memory Systems
Publisher	Association for Computing Machinery
Pages	77-85
Number of pages	9
ISBN (Electronic)	9781450388993
DOIs	https://doi.org/10.1145/3422575.3422779
State	Published - 28 Sep 2020
Event	2020 International Symposium on Memory Systems, MEMSYS 2020 - Washington, United States Duration: 28 Sep 2020 → 1 Oct 2020

Publication series

Name	ACM International Conference Proceeding Series

Conference

Conference	2020 International Symposium on Memory Systems, MEMSYS 2020
Country/Territory	United States
City	Washington
Period	28/09/20 → 1/10/20

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy
SDG 9 Industry, Innovation, and Infrastructure

Keywords

3D NAND Flash
Deep neural network
compute-in-memory
hardware accelerator

Access to Document

10.1145/3422575.3422779

Cite this

@inproceedings{d1b576fb4bff4883a65123699328d09d,

title = "Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine",

abstract = "3D NAND Flash memory has been proposed as an attractive candidate of inference engine for deep neural network (DNN) owing to its ultra-high density and commercially matured fabrication technology. However, the peripheral circuits require to be modified to enable compute-in-memory (CIM) and the chip architectures need to be redesigned for an optimized dataflow. In this work, we present a design of 3D NAND-CIM accelerator based on the macro parameters from an industry-grade prototype chip. The DNN inference performance is evaluated using the DNN+ NeuroSim framework. To exploit the ultra-high density of 3D NAND Flash, both inputs and weights duplication strategies are introduced to improve the throughput. The benchmarking on a variety of VGG and ResNet networks was performed across technological candidates for CIM including SRAM, RRAM and 3D NAND. Compared to similar designs with SRAM or RRAM, the result shows that 3D NAND based CIM design can achieve not only 17-24\% chip size but also 1.9-2.7 times more competitive energy efficiency for 8-bit precision inference.",

keywords = "3D NAND Flash, Deep neural network, compute-in-memory, hardware accelerator",

author = "Wonbo Shim and Hongwu Jiang and Xiaochen Peng and Shimeng Yu",

note = "Publisher Copyright: {\textcopyright} 2020 ACM.; 2020 International Symposium on Memory Systems, MEMSYS 2020 ; Conference date: 28-09-2020 Through 01-10-2020",

year = "2020",

month = sep,

day = "28",

doi = "10.1145/3422575.3422779",

language = "English",

series = "ACM International Conference Proceeding Series",

publisher = "Association for Computing Machinery",

pages = "77--85",

booktitle = "MEMSYS 2020 - Proceedings of the International Symposium on Memory Systems",

}

Shim, W, Jiang, H, Peng, X & Yu, S 2020, Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine. in MEMSYS 2020 - Proceedings of the International Symposium on Memory Systems., 3422779, ACM International Conference Proceeding Series, Association for Computing Machinery, pp. 77-85, 2020 International Symposium on Memory Systems, MEMSYS 2020, Washington, United States, 28/09/20. https://doi.org/10.1145/3422575.3422779

Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine. / Shim, Wonbo; Jiang, Hongwu; Peng, Xiaochen et al.
MEMSYS 2020 - Proceedings of the International Symposium on Memory Systems. Association for Computing Machinery, 2020. p. 77-85 3422779 (ACM International Conference Proceeding Series).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine

AU - Shim, Wonbo

AU - Jiang, Hongwu

AU - Peng, Xiaochen

AU - Yu, Shimeng

PY - 2020/9/28

Y1 - 2020/9/28

N2 - 3D NAND Flash memory has been proposed as an attractive candidate of inference engine for deep neural network (DNN) owing to its ultra-high density and commercially matured fabrication technology. However, the peripheral circuits require to be modified to enable compute-in-memory (CIM) and the chip architectures need to be redesigned for an optimized dataflow. In this work, we present a design of 3D NAND-CIM accelerator based on the macro parameters from an industry-grade prototype chip. The DNN inference performance is evaluated using the DNN+ NeuroSim framework. To exploit the ultra-high density of 3D NAND Flash, both inputs and weights duplication strategies are introduced to improve the throughput. The benchmarking on a variety of VGG and ResNet networks was performed across technological candidates for CIM including SRAM, RRAM and 3D NAND. Compared to similar designs with SRAM or RRAM, the result shows that 3D NAND based CIM design can achieve not only 17-24% chip size but also 1.9-2.7 times more competitive energy efficiency for 8-bit precision inference.

AB - 3D NAND Flash memory has been proposed as an attractive candidate of inference engine for deep neural network (DNN) owing to its ultra-high density and commercially matured fabrication technology. However, the peripheral circuits require to be modified to enable compute-in-memory (CIM) and the chip architectures need to be redesigned for an optimized dataflow. In this work, we present a design of 3D NAND-CIM accelerator based on the macro parameters from an industry-grade prototype chip. The DNN inference performance is evaluated using the DNN+ NeuroSim framework. To exploit the ultra-high density of 3D NAND Flash, both inputs and weights duplication strategies are introduced to improve the throughput. The benchmarking on a variety of VGG and ResNet networks was performed across technological candidates for CIM including SRAM, RRAM and 3D NAND. Compared to similar designs with SRAM or RRAM, the result shows that 3D NAND based CIM design can achieve not only 17-24% chip size but also 1.9-2.7 times more competitive energy efficiency for 8-bit precision inference.

KW - 3D NAND Flash

KW - Deep neural network

KW - compute-in-memory

KW - hardware accelerator

UR - https://www.scopus.com/pages/publications/85100325239

U2 - 10.1145/3422575.3422779

DO - 10.1145/3422575.3422779

M3 - Conference contribution

AN - SCOPUS:85100325239

T3 - ACM International Conference Proceeding Series

SP - 77

EP - 85

BT - MEMSYS 2020 - Proceedings of the International Symposium on Memory Systems

PB - Association for Computing Machinery

T2 - 2020 International Symposium on Memory Systems, MEMSYS 2020

Y2 - 28 September 2020 through 1 October 2020

ER -

Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference Engine

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

Other files and links

Fingerprint

Cite this