TY - GEN
T1 - BEOL-compatible Non-Volatile Capacitive Synapse with ALD W-doped In2O3 Semiconductor Layer
AU - Lee, Junmo
AU - Zhang, Chengyang
AU - Shon, Minji
AU - Read, James
AU - Deng, Sunbin
AU - Phadke, Omkar
AU - Ravindran, Prasanna Venkatesan
AU - Tian, Mengkun
AU - Luo, Yuan Chun
AU - Kim, Tae Hyeon
AU - Khan, Asif Islam
AU - Datta, Suman
AU - Yu, Shimeng
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - We experimentally demonstrate BEOL-compatible metal-ferroelectric-semiconductor (MFS)-type non-volatile capacitive (nvCAP) synapse with atomic layer deposition (ALD)-grown W-doped In2O3 (IWO) as the semiconductor layer. For the first time, ALD with in-situ W doping technique is utilized for the In2O3 layer deposition. We propose W doping and overlap area engineering to achieve capacitance on/off ratio of ~24 under non-destructive read scheme (Vread = 0 V), a record value among reported BEOL-compatible capacitive synapses. Array-level performance benchmark of the compute-in-memory (CIM) hardware consisting of 3D scaled ALD IWO-based nvCAPs suggests 24.4× figure-of-merit (=TOPS/W×TOPS/mm2) improvement over state-of-the art resistive synapse thanks to dynamic-power only charge-domain computation and 3D BEOL integration.
AB - We experimentally demonstrate BEOL-compatible metal-ferroelectric-semiconductor (MFS)-type non-volatile capacitive (nvCAP) synapse with atomic layer deposition (ALD)-grown W-doped In2O3 (IWO) as the semiconductor layer. For the first time, ALD with in-situ W doping technique is utilized for the In2O3 layer deposition. We propose W doping and overlap area engineering to achieve capacitance on/off ratio of ~24 under non-destructive read scheme (Vread = 0 V), a record value among reported BEOL-compatible capacitive synapses. Array-level performance benchmark of the compute-in-memory (CIM) hardware consisting of 3D scaled ALD IWO-based nvCAPs suggests 24.4× figure-of-merit (=TOPS/W×TOPS/mm2) improvement over state-of-the art resistive synapse thanks to dynamic-power only charge-domain computation and 3D BEOL integration.
UR - https://www.scopus.com/pages/publications/86000024242
U2 - 10.1109/IEDM50854.2024.10873481
DO - 10.1109/IEDM50854.2024.10873481
M3 - Conference contribution
AN - SCOPUS:86000024242
T3 - Technical Digest - International Electron Devices Meeting, IEDM
BT - 2024 IEEE International Electron Devices Meeting, IEDM 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2024 IEEE International Electron Devices Meeting, IEDM 2024
Y2 - 7 December 2024 through 11 December 2024
ER -