Bit-width reduction in write counters for wear leveling in a phase-change memory system

Phase-change memory (PCM) has garnered attention as a next-generation memory owing to its non-volatility and scalability. However, PCM wears out under excessive write accesses; hence, it must be supported by wear-leveling algorithms to uniformly distribute the number of accesses across the entire address space. Table-based wear leveling is one of the representative algorithms that stores a write counter for each address region for remapping frequently accessed addresses with lower overhead; however, write counters consume resources in a PCM system. In this study, a bit-width reduction method in write counters for wear leveling is proposed, where the method utilizes a stochastic finite-state machine to probabilistically count the number of write accesses. The proposed method shows only a 1.2% lifetime degradation using six bits for each counter, with 40% fewer resources spent on write counters when the endurance of a 4KB block is 1E+06.