Bonding-Based Method to Prevent Contamination in Polymer Integration for Semiconductor Applications

The direct deposition of polymer dielectrics in CMOS fabrication tools is often restricted due to contamination concerns arising from unreacted monomers and process by-products. To enable contamination-free polymer integration, this study employs an external deposition approach in which the organic polymer dielectric pV3D3 is deposited outside the fabrication line and subsequently incorporated into the device structure through a bonding step. This method prevents polymer exposure to process equipment while leveraging the favorable electrical characteristics of pV3D3. The bonded structures were evaluated through electrical and structural analyses. pV3D3 exhibited stable insulating performance in current–voltage (I-V) and capacitance–voltage (C-V) measurements. Scanning acoustic tomography (SAT) and atomic force microscopy (AFM) confirmed void-free bonding interfaces and an atomically smooth surface (~0.3-nm rms) suitable for bonding. Transmission electron microscopy (TEM) and energy-dispersive spectroscopy (EDS) revealed localized Cu penetration into pV3D3 only after high-voltage stress, indicating that the bonding step itself did not induce material degradation. These results demonstrate that externally deposited pV3D3 can be reliably integrated into semiconductor devices via bonding, providing a practical route toward contamination-free dielectric incorporation in advanced packaging applications.