TY - GEN
T1 - Buffer-integrated-cache
T2 - 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
AU - Fajardo, Carlos Flores
AU - Fang, Zhen
AU - Iyer, Ravi
AU - Garcia, German Fabila
AU - Lee, Seung Eun
AU - Zhao, Li
PY - 2011
Y1 - 2011
N2 - In an SoC, building local storage in each accelerator is area inefficient due to the low average utilization. In this paper, we present design and implementation of Buffer-integrated-Caching (BiC), which allows many buffers to be instantiated simultaneously in caches. BiC enables cores to view portions of the SRAM as cache while accelerators access other portions of the SRAM as private buffers. We demonstrate the cost-effectiveness of BiC based on a recognition MPSoC that includes two Pentium™ cores, an Augmented Reality accelerator and a speech recognition accelerator. With 3% extra area added to the baseline L2 cache, BiC eliminates the need to build 215KB dedicated SRAM for the accelerators, while increasing total cache misses by no more than 0.3%.
AB - In an SoC, building local storage in each accelerator is area inefficient due to the low average utilization. In this paper, we present design and implementation of Buffer-integrated-Caching (BiC), which allows many buffers to be instantiated simultaneously in caches. BiC enables cores to view portions of the SRAM as cache while accelerators access other portions of the SRAM as private buffers. We demonstrate the cost-effectiveness of BiC based on a recognition MPSoC that includes two Pentium™ cores, an Augmented Reality accelerator and a speech recognition accelerator. With 3% extra area added to the baseline L2 cache, BiC eliminates the need to build 215KB dedicated SRAM for the accelerators, while increasing total cache misses by no more than 0.3%.
KW - Accelerator
KW - Cache
KW - Memory
KW - System-on-Chip
UR - https://www.scopus.com/pages/publications/80052679438
M3 - Conference contribution
AN - SCOPUS:80052679438
SN - 9781450306362
T3 - Proceedings - Design Automation Conference
SP - 966
EP - 971
BT - 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
Y2 - 5 June 2011 through 9 June 2011
ER -