Capacitive Synaptor with Overturned Charge Injection for Compute-in-Memory

Choong Ki Kim; Omkar Phadke; Tae Hyeon Kim; Myung Su Kim; Ji Man Yu; Min Soo Yoo; Yang Kyu Choi; Shimeng Yu

doi:10.1109/LED.2024.3382497

Capacitive Synaptor with Overturned Charge Injection for Compute-in-Memory

Choong Ki Kim, Omkar Phadke, Tae Hyeon Kim, Myung Su Kim, Ji Man Yu, Min Soo Yoo, Yang Kyu Choi, Shimeng Yu

Dept. of Semiconductor Engineering

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On-and off-state capacitances (Con and Coff) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 10⁷ cycles and retention time of 10⁴ sec.

Original language	English
Pages (from-to)	929-932
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	45
Issue number	5
DOIs	https://doi.org/10.1109/LED.2024.3382497
State	Published - 1 May 2024

Keywords

capacitive synapse
Compute-in-memory
cycling endurance
floating gate
retention

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Access to Document

10.1109/LED.2024.3382497

Cite this

@article{d186d686d5e8436b9d314be7fb5b4347,

title = "Capacitive Synaptor with Overturned Charge Injection for Compute-in-Memory",

abstract = "A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On-and off-state capacitances (Con and Coff) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 107 cycles and retention time of 104 sec.",

keywords = "capacitive synapse, Compute-in-memory, cycling endurance, floating gate, retention",

author = "Kim, {Choong Ki} and Omkar Phadke and Kim, {Tae Hyeon} and Kim, {Myung Su} and Yu, {Ji Man} and Yoo, {Min Soo} and Choi, {Yang Kyu} and Shimeng Yu",

note = "Publisher Copyright: {\textcopyright} 1980-2012 IEEE.",

year = "2024",

month = may,

day = "1",

doi = "10.1109/LED.2024.3382497",

language = "English",

volume = "45",

pages = "929--932",

journal = "IEEE Electron Device Letters",

issn = "0741-3106",

number = "5",

}

TY - JOUR

T1 - Capacitive Synaptor with Overturned Charge Injection for Compute-in-Memory

AU - Kim, Choong Ki

AU - Phadke, Omkar

AU - Kim, Tae Hyeon

AU - Kim, Myung Su

AU - Yu, Ji Man

AU - Yoo, Min Soo

AU - Choi, Yang Kyu

AU - Yu, Shimeng

PY - 2024/5/1

Y1 - 2024/5/1

N2 - A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On-and off-state capacitances (Con and Coff) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 107 cycles and retention time of 104 sec.

AB - A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On-and off-state capacitances (Con and Coff) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 107 cycles and retention time of 104 sec.

KW - capacitive synapse

KW - Compute-in-memory

KW - cycling endurance

KW - floating gate

KW - retention

UR - http://www.scopus.com/inward/record.url?scp=85189500895&partnerID=8YFLogxK

U2 - 10.1109/LED.2024.3382497

DO - 10.1109/LED.2024.3382497

M3 - Article

AN - SCOPUS:85189500895

SN - 0741-3106

VL - 45

SP - 929

EP - 932

JO - IEEE Electron Device Letters

JF - IEEE Electron Device Letters

IS - 5

ER -

Capacitive Synaptor with Overturned Charge Injection for Compute-in-Memory

Abstract

Keywords

UN SDGs

Access to Document

Other files and links

Fingerprint

Cite this