Capacitive Synaptor with Overturned Charge Injection for Compute-in-Memory

Choong Ki Kim; Omkar Phadke; Tae Hyeon Kim; Myung Su Kim; Ji Man Yu; Min Soo Yoo; Yang Kyu Choi; Shimeng Yu

doi:10.1109/LED.2024.3382497

Capacitive Synaptor with Overturned Charge Injection for Compute-in-Memory

Choong Ki Kim
, Omkar Phadke
, Tae Hyeon Kim
, Myung Su Kim
, Ji Man Yu
, Min Soo Yoo
, Yang Kyu Choi
, Shimeng Yu

Dept. of Semiconductor Engineering

SK Corporation
Georgia Institute of Technology
Korea Advanced Institute of Science and Technology

Research output: Contribution to journal › Article › peer-review

4 Scopus citations

Abstract

A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On-and off-state capacitances (Con and Coff) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 10⁷ cycles and retention time of 10⁴ sec.

Original language	English
Pages (from-to)	929-932
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	45
Issue number	5
DOIs	https://doi.org/10.1109/LED.2024.3382497
State	Published - 1 May 2024

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

capacitive synapse
Compute-in-memory
cycling endurance
floating gate
retention

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10.1109/LED.2024.3382497

Cite this

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abstract = "A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On-and off-state capacitances (Con and Coff) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 107 cycles and retention time of 104 sec.",

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AU - Yu, Ji Man

AU - Yoo, Min Soo

AU - Choi, Yang Kyu

AU - Yu, Shimeng

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AB - A capacitive synaptic transistor (synaptor) compatible with the fabrication process of conventional Flash memory is proposed for compute-in-memory (CIM) array cells to support energy-efficient inference operations. This synaptor demonstrates the highly reliable endurance characteristic of program/erase (P/E) due to overturned charge injection occurring between a control gate (CG) and a floating gate (FG) rather than between the FG and a channel. On-and off-state capacitances (Con and Coff) are determined by the area ratio of CG and FG. After optimizing the pulse conditions, we achieved the P/E endurance of at least 107 cycles and retention time of 104 sec.

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KW - retention

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Capacitive Synaptor with Overturned Charge Injection for Compute-in-Memory

Abstract

UN SDGs

Keywords

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