Chopped anodic 펄스 제어를 이용한 charge balanced 뇌신경 자극 집적회로

This paper presents a neural stimulator integrated circuit(IC) using chopped pulse waveform for high power efficiency and charge balancing. The proposed IC is designed using 0.18-μm standard CMOS process and consists of electric stimulation circuit and charge balancing circuit. Transistor stacking and dynamic gate biasing technique are used to protect the output current driver and charge balancing circuit from high voltage stress. The proposed system has flexibility to select two types of stimulation waveform according to the situation. A very simple digital logic circuit consisting of a comparator and D-Latch performs safe charge balancing to prevent the accumulation of residual potential on the electrodes.