Circulating Current Suppression DPWM for Two Parallel NPC Inverters

In parallel NPC inverters, the reduction of circulating current is one of the major concerns since it is closely related to the performance of parallel NPC inverters, such as efficiency, power quality, and reliability. Previous studies have proposed various PWM methods to reduce circulating current. However, there are inherent trade-offs among the circulating current suppression and other performances, such as output current THD, efficiency, and thermal loadings of power devices and DC-link capacitors. This paper proposes a PWM method for the dual parallel NPC inverters operated at high modulation indices to reduce the circulating current and improve the output current THD. In addition, the proposed method maintains the other performances of the inverter, such as efficiency and thermal loadings on the power devices and DC-link capacitors, similar to the state-of-the-art PWM methods. The feasibility and effectiveness of the proposed PWM method are verified through the simulations by comparing it with the state-of-the-art PWM methods for the parallel NPC inverters.