Compute-in-Memory: From Device Innovation to 3D System Integration

Shimeng Yu; Wonbo Shim; Jae Hur; Yuan Chun Luo; Gihun Choe; Wantong Li; Anni Lu; Xiaochen Peng

doi:10.1109/ESSDERC53440.2021.9631765

Compute-in-Memory: From Device Innovation to 3D System Integration

Shimeng Yu
, Wonbo Shim
, Jae Hur
, Yuan Chun Luo
, Gihun Choe
, Wantong Li
, Anni Lu
, Xiaochen Peng

Dept. of Electrical and Information Engineering

Georgia Institute of Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

12 Scopus citations

Abstract

Compute-in-memory (CIM) hardware accelerator has been emerged as a promising paradigm for executing the artificial intelligence (AI) tasks owing to its superior energy efficiency. In this keynote presentation, we survey recent progresses of CIM technologies from device-level demonstration to system-level benchmark. First, the ferroelectric devices (FeM-FinFET., ferroelectric non-volatile capacitor) are introduced for resistive and capacitive read-out mechanism for crossbar arrays. Second, resistive random access memory (RRAM) based CIM macro has been taped-out into prototype chips in commercial foundry process and the related NeuroSim validation with measured silicon data is shown. Last, heterogeneous 3D integration scheme for SRAM, RRAM and 3D NAND tiers and logic tier is proposed.

Original language	English
Title of host publication	ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings
Publisher	Editions Frontieres
Pages	21-28
Number of pages	8
ISBN (Electronic)	9781665437479
DOIs	https://doi.org/10.1109/ESSDERC53440.2021.9631765
State	Published - 2021
Event	51st IEEE European Solid-State Device Research Conference, ESSDERC 2021 - Virtual, Online, France Duration: 6 Sep 2021 → 9 Sep 2021

Publication series

Name	European Solid-State Device Research Conference
Volume	2021-September
ISSN (Print)	1930-8876

Conference

Conference	51st IEEE European Solid-State Device Research Conference, ESSDERC 2021
Country/Territory	France
City	Virtual, Online
Period	6/09/21 → 9/09/21

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 7 Affordable and Clean Energy

Keywords

compute-in-memory
ferroelectric device
hardware accelerator
heterogeneous 3D integration
resistive random access memory (RRAM)

Access to Document

10.1109/ESSDERC53440.2021.9631765

Cite this

Yu, S., Shim, W., Hur, J., Luo, Y. C., Choe, G., Li, W., Lu, A., & Peng, X. (2021). Compute-in-Memory: From Device Innovation to 3D System Integration. In ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings (pp. 21-28). (European Solid-State Device Research Conference; Vol. 2021-September). Editions Frontieres. https://doi.org/10.1109/ESSDERC53440.2021.9631765

@inproceedings{ddb63e1b78554a9f9aaad4a8e44a98c3,

title = "Compute-in-Memory: From Device Innovation to 3D System Integration",

abstract = "Compute-in-memory (CIM) hardware accelerator has been emerged as a promising paradigm for executing the artificial intelligence (AI) tasks owing to its superior energy efficiency. In this keynote presentation, we survey recent progresses of CIM technologies from device-level demonstration to system-level benchmark. First, the ferroelectric devices (FeM-FinFET., ferroelectric non-volatile capacitor) are introduced for resistive and capacitive read-out mechanism for crossbar arrays. Second, resistive random access memory (RRAM) based CIM macro has been taped-out into prototype chips in commercial foundry process and the related NeuroSim validation with measured silicon data is shown. Last, heterogeneous 3D integration scheme for SRAM, RRAM and 3D NAND tiers and logic tier is proposed.",

keywords = "compute-in-memory, ferroelectric device, hardware accelerator, heterogeneous 3D integration, resistive random access memory (RRAM)",

author = "Shimeng Yu and Wonbo Shim and Jae Hur and Luo, \{Yuan Chun\} and Gihun Choe and Wantong Li and Anni Lu and Xiaochen Peng",

note = "Publisher Copyright: {\textcopyright} 2021 IEEE.; 51st IEEE European Solid-State Device Research Conference, ESSDERC 2021 ; Conference date: 06-09-2021 Through 09-09-2021",

year = "2021",

doi = "10.1109/ESSDERC53440.2021.9631765",

language = "English",

series = "European Solid-State Device Research Conference",

publisher = "Editions Frontieres",

pages = "21--28",

booktitle = "ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings",

}

Yu, S, Shim, W, Hur, J, Luo, YC, Choe, G, Li, W, Lu, A & Peng, X 2021, Compute-in-Memory: From Device Innovation to 3D System Integration. in ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings. European Solid-State Device Research Conference, vol. 2021-September, Editions Frontieres, pp. 21-28, 51st IEEE European Solid-State Device Research Conference, ESSDERC 2021, Virtual, Online, France, 6/09/21. https://doi.org/10.1109/ESSDERC53440.2021.9631765

Compute-in-Memory: From Device Innovation to 3D System Integration. / Yu, Shimeng; Shim, Wonbo; Hur, Jae et al.
ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings. Editions Frontieres, 2021. p. 21-28 (European Solid-State Device Research Conference; Vol. 2021-September).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Compute-in-Memory

T2 - 51st IEEE European Solid-State Device Research Conference, ESSDERC 2021

AU - Yu, Shimeng

AU - Shim, Wonbo

AU - Hur, Jae

AU - Luo, Yuan Chun

AU - Choe, Gihun

AU - Li, Wantong

AU - Lu, Anni

AU - Peng, Xiaochen

PY - 2021

Y1 - 2021

N2 - Compute-in-memory (CIM) hardware accelerator has been emerged as a promising paradigm for executing the artificial intelligence (AI) tasks owing to its superior energy efficiency. In this keynote presentation, we survey recent progresses of CIM technologies from device-level demonstration to system-level benchmark. First, the ferroelectric devices (FeM-FinFET., ferroelectric non-volatile capacitor) are introduced for resistive and capacitive read-out mechanism for crossbar arrays. Second, resistive random access memory (RRAM) based CIM macro has been taped-out into prototype chips in commercial foundry process and the related NeuroSim validation with measured silicon data is shown. Last, heterogeneous 3D integration scheme for SRAM, RRAM and 3D NAND tiers and logic tier is proposed.

AB - Compute-in-memory (CIM) hardware accelerator has been emerged as a promising paradigm for executing the artificial intelligence (AI) tasks owing to its superior energy efficiency. In this keynote presentation, we survey recent progresses of CIM technologies from device-level demonstration to system-level benchmark. First, the ferroelectric devices (FeM-FinFET., ferroelectric non-volatile capacitor) are introduced for resistive and capacitive read-out mechanism for crossbar arrays. Second, resistive random access memory (RRAM) based CIM macro has been taped-out into prototype chips in commercial foundry process and the related NeuroSim validation with measured silicon data is shown. Last, heterogeneous 3D integration scheme for SRAM, RRAM and 3D NAND tiers and logic tier is proposed.

KW - compute-in-memory

KW - ferroelectric device

KW - hardware accelerator

KW - heterogeneous 3D integration

KW - resistive random access memory (RRAM)

UR - https://www.scopus.com/pages/publications/85123396893

U2 - 10.1109/ESSDERC53440.2021.9631765

DO - 10.1109/ESSDERC53440.2021.9631765

M3 - Conference contribution

AN - SCOPUS:85123396893

T3 - European Solid-State Device Research Conference

SP - 21

EP - 28

BT - ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference, Proceedings

PB - Editions Frontieres

Y2 - 6 September 2021 through 9 September 2021

ER -

Compute-in-Memory: From Device Innovation to 3D System Integration

Abstract

Publication series

Conference

UN SDGs

Keywords

Access to Document

Other files and links

Fingerprint

Cite this