Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture

Joungmin Park; Seongmo An; Jinyeol Kim; Seung Eun Lee

doi:10.1109/ISOCC59558.2023.10396060

Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture

Joungmin Park, Seongmo An, Jinyeol Kim, Seung Eun Lee

Electronic Engineering Program

Seoul National University of Science and Technology (SNUST)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

Convolution operation is a crucial technique in the field of artificial intelligence (AI), particularly in image processing-based applications. However, a significant amount of computation time is required to perform an operation on a vast amount of data. The conventional operation processing method of the systolic array architecture tends to accelerate the speed of convolution operations by reusing only the weight data. To minimize data movement time, we propose a systolic array architecture that partially reuses the input feature map. Compared to the conventional systolic array accelerator, the proposed architecture demonstrated a throughput improvement of ×6.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference 2023, ISOCC 2023
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	319-320
Number of pages	2
ISBN (Electronic)	9798350327038
DOIs	https://doi.org/10.1109/ISOCC59558.2023.10396060
State	Published - 2023
Event	20th International SoC Design Conference, ISOCC 2023 - Jeju, Korea, Republic of Duration: 25 Oct 2023 → 28 Oct 2023

Publication series

Name	Proceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Conference	20th International SoC Design Conference, ISOCC 2023
Country/Territory	Korea, Republic of
City	Jeju
Period	25/10/23 → 28/10/23

Keywords

accelerator
convolution
data reuse
systolic array

Access to Document

10.1109/ISOCC59558.2023.10396060

Cite this

Park, J., An, S., Kim, J., & Lee, S. E. (2023). Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture. In Proceedings - International SoC Design Conference 2023, ISOCC 2023 (pp. 319-320). (Proceedings - International SoC Design Conference 2023, ISOCC 2023). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC59558.2023.10396060

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title = "Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture",

abstract = "Convolution operation is a crucial technique in the field of artificial intelligence (AI), particularly in image processing-based applications. However, a significant amount of computation time is required to perform an operation on a vast amount of data. The conventional operation processing method of the systolic array architecture tends to accelerate the speed of convolution operations by reusing only the weight data. To minimize data movement time, we propose a systolic array architecture that partially reuses the input feature map. Compared to the conventional systolic array accelerator, the proposed architecture demonstrated a throughput improvement of ×6.",

keywords = "accelerator, convolution, data reuse, systolic array",

author = "Joungmin Park and Seongmo An and Jinyeol Kim and Lee, {Seung Eun}",

note = "Publisher Copyright: {\textcopyright} 2023 IEEE.; 20th International SoC Design Conference, ISOCC 2023 ; Conference date: 25-10-2023 Through 28-10-2023",

year = "2023",

doi = "10.1109/ISOCC59558.2023.10396060",

language = "English",

series = "Proceedings - International SoC Design Conference 2023, ISOCC 2023",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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booktitle = "Proceedings - International SoC Design Conference 2023, ISOCC 2023",

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Park, J, An, S, Kim, J & Lee, SE 2023, Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture. in Proceedings - International SoC Design Conference 2023, ISOCC 2023. Proceedings - International SoC Design Conference 2023, ISOCC 2023, Institute of Electrical and Electronics Engineers Inc., pp. 319-320, 20th International SoC Design Conference, ISOCC 2023, Jeju, Korea, Republic of, 25/10/23. https://doi.org/10.1109/ISOCC59558.2023.10396060

Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture. / Park, Joungmin; An, Seongmo; Kim, Jinyeol et al.
Proceedings - International SoC Design Conference 2023, ISOCC 2023. Institute of Electrical and Electronics Engineers Inc., 2023. p. 319-320 (Proceedings - International SoC Design Conference 2023, ISOCC 2023).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

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T1 - Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture

AU - Park, Joungmin

AU - An, Seongmo

AU - Kim, Jinyeol

AU - Lee, Seung Eun

PY - 2023

Y1 - 2023

N2 - Convolution operation is a crucial technique in the field of artificial intelligence (AI), particularly in image processing-based applications. However, a significant amount of computation time is required to perform an operation on a vast amount of data. The conventional operation processing method of the systolic array architecture tends to accelerate the speed of convolution operations by reusing only the weight data. To minimize data movement time, we propose a systolic array architecture that partially reuses the input feature map. Compared to the conventional systolic array accelerator, the proposed architecture demonstrated a throughput improvement of ×6.

AB - Convolution operation is a crucial technique in the field of artificial intelligence (AI), particularly in image processing-based applications. However, a significant amount of computation time is required to perform an operation on a vast amount of data. The conventional operation processing method of the systolic array architecture tends to accelerate the speed of convolution operations by reusing only the weight data. To minimize data movement time, we propose a systolic array architecture that partially reuses the input feature map. Compared to the conventional systolic array accelerator, the proposed architecture demonstrated a throughput improvement of ×6.

KW - accelerator

KW - convolution

KW - data reuse

KW - systolic array

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U2 - 10.1109/ISOCC59558.2023.10396060

DO - 10.1109/ISOCC59558.2023.10396060

M3 - Conference contribution

AN - SCOPUS:85184822527

T3 - Proceedings - International SoC Design Conference 2023, ISOCC 2023

SP - 319

EP - 320

BT - Proceedings - International SoC Design Conference 2023, ISOCC 2023

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 20th International SoC Design Conference, ISOCC 2023

Y2 - 25 October 2023 through 28 October 2023

ER -

Continuous Convolution Accelerator with Data Reuse based on Systolic Architecture

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Keywords

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