Cycle accurate power and performance simulator for design space exploration on a many-core platform

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Abstract

As the computation demands increases to meet the design requirements for computation-intensive applications, the pressure to develop high performance parallel processors on a chip is increasing. However, software supports that enable harnessing parallel computing power of this type of architecture have not followed suit and it has become an important stumbling block for future many core application developments. In this paper, we introduce a cycle-accurate simulator for parallel programming on many-core platform, enabling fast design space exploration.

Original languageEnglish
Title of host publicationAdvances in Computer Science, Environment, Ecoinformatics, and Education - International Conference, CSEE 2011, Proceedings
Pages169-175
Number of pages7
EditionPART 2
DOIs
StatePublished - 2011
EventInternational Conference on Advances in Computer Science, Environment, Ecoinformatics, and Education, CSEE 2011 - Wuhan, China
Duration: 21 Aug 201122 Aug 2011

Publication series

NameCommunications in Computer and Information Science
NumberPART 2
Volume215 CCIS
ISSN (Print)1865-0929

Conference

ConferenceInternational Conference on Advances in Computer Science, Environment, Ecoinformatics, and Education, CSEE 2011
Country/TerritoryChina
CityWuhan
Period21/08/1122/08/11

Keywords

  • design space exploration
  • Multiprocessor
  • Network-on-Chip
  • power model
  • simulator

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