Demonstration of bias scheme for ferroelectric field-effect transistor (FeFET) based AND array operation

Shinhee Kim; Jae Yeon Park; Dong Keun Lee; Hyungju Noh; Tae Hyeon Kim; Sihyun Kim; Sangwan Kim

doi:10.1016/j.sse.2024.108917

Demonstration of bias scheme for ferroelectric field-effect transistor (FeFET) based AND array operation

Shinhee Kim, Jae Yeon Park, Dong Keun Lee, Hyungju Noh, Tae Hyeon Kim, Sihyun Kim, Sangwan Kim

Dept. of Semiconductor Engineering

Sogang University

Research output: Contribution to journal › Article › peer-review

Abstract

In this study, we experimentally demonstrated a simplified write inhibition bias scheme for a ferroelectric field-effect transistor (FeFET) based AND array, which is the promising energy- and area-efficient memory. The write inhibition scheme that only employs the bit line (BL) voltages was optimized through the single cell FeFET measurements. The program and erase operations were confirmed to be apparently inhibited with the BL/source line (SL) voltages of 3.5 V/0 V, respectively. The suggested inhibition bias scheme was then applied to the 16 × 16 FeFET AND array for demonstrating its validity. It was clearly verified that selective program/erase operations were possible without modulating the SL voltages, suggesting its benefits in terms of area-efficiency.

Original language	English
Article number	108917
Journal	Solid-State Electronics
Volume	216
DOIs	https://doi.org/10.1016/j.sse.2024.108917
State	Published - Jun 2024

Keywords

AND array
Bias scheme
Ferroelectric field-effect transistor
Low-power

Access to Document

10.1016/j.sse.2024.108917

Cite this

@article{ba7bf75714e8414ea070edae7548d827,

title = "Demonstration of bias scheme for ferroelectric field-effect transistor (FeFET) based AND array operation",

abstract = "In this study, we experimentally demonstrated a simplified write inhibition bias scheme for a ferroelectric field-effect transistor (FeFET) based AND array, which is the promising energy- and area-efficient memory. The write inhibition scheme that only employs the bit line (BL) voltages was optimized through the single cell FeFET measurements. The program and erase operations were confirmed to be apparently inhibited with the BL/source line (SL) voltages of 3.5 V/0 V, respectively. The suggested inhibition bias scheme was then applied to the 16 × 16 FeFET AND array for demonstrating its validity. It was clearly verified that selective program/erase operations were possible without modulating the SL voltages, suggesting its benefits in terms of area-efficiency.",

keywords = "AND array, Bias scheme, Ferroelectric field-effect transistor, Low-power",

author = "Shinhee Kim and Park, \{Jae Yeon\} and Lee, \{Dong Keun\} and Hyungju Noh and Kim, \{Tae Hyeon\} and Sihyun Kim and Sangwan Kim",

note = "Publisher Copyright: {\textcopyright} 2024 Elsevier Ltd",

year = "2024",

month = jun,

doi = "10.1016/j.sse.2024.108917",

language = "English",

volume = "216",

journal = "Solid-State Electronics",

issn = "0038-1101",

}

TY - JOUR

T1 - Demonstration of bias scheme for ferroelectric field-effect transistor (FeFET) based AND array operation

AU - Kim, Shinhee

AU - Park, Jae Yeon

AU - Lee, Dong Keun

AU - Noh, Hyungju

AU - Kim, Tae Hyeon

AU - Kim, Sihyun

AU - Kim, Sangwan

PY - 2024/6

Y1 - 2024/6

N2 - In this study, we experimentally demonstrated a simplified write inhibition bias scheme for a ferroelectric field-effect transistor (FeFET) based AND array, which is the promising energy- and area-efficient memory. The write inhibition scheme that only employs the bit line (BL) voltages was optimized through the single cell FeFET measurements. The program and erase operations were confirmed to be apparently inhibited with the BL/source line (SL) voltages of 3.5 V/0 V, respectively. The suggested inhibition bias scheme was then applied to the 16 × 16 FeFET AND array for demonstrating its validity. It was clearly verified that selective program/erase operations were possible without modulating the SL voltages, suggesting its benefits in terms of area-efficiency.

AB - In this study, we experimentally demonstrated a simplified write inhibition bias scheme for a ferroelectric field-effect transistor (FeFET) based AND array, which is the promising energy- and area-efficient memory. The write inhibition scheme that only employs the bit line (BL) voltages was optimized through the single cell FeFET measurements. The program and erase operations were confirmed to be apparently inhibited with the BL/source line (SL) voltages of 3.5 V/0 V, respectively. The suggested inhibition bias scheme was then applied to the 16 × 16 FeFET AND array for demonstrating its validity. It was clearly verified that selective program/erase operations were possible without modulating the SL voltages, suggesting its benefits in terms of area-efficiency.

KW - AND array

KW - Bias scheme

KW - Ferroelectric field-effect transistor

KW - Low-power

UR - http://www.scopus.com/inward/record.url?scp=85189516091&partnerID=8YFLogxK

U2 - 10.1016/j.sse.2024.108917

DO - 10.1016/j.sse.2024.108917

M3 - Article

AN - SCOPUS:85189516091

SN - 0038-1101

VL - 216

JO - Solid-State Electronics

JF - Solid-State Electronics

M1 - 108917

ER -

Demonstration of bias scheme for ferroelectric field-effect transistor (FeFET) based AND array operation

Abstract

Keywords

Access to Document

Other files and links

Fingerprint

Cite this