Design of 2T DRAM Cell With Surrounding Poly-Si Capacitor for Enhanced Retention and Mitigated Coupling Effect

Two-transistors-zero-capacitor (2T0C) DRAM-based processing-in-memory (PIM) system experiences retention degradation and capacitive coupling effects because of its volatile characteristics and capacitorless structure. These challenges result in degraded reliability and significant energy consumption due to frequent refresh operations. In this work, we propose a cell structure with surrounding polycrystalline silicon capacitor (poly-Cap.) to enhance the storage node capacitance of the vertical-transistor on gate (VTG) DRAM cell introduced in our previous work. The poly-Cap. improves the retention characteristics and mitigates the capacitive coupling effects while maintaining its unit cell area. We modeled the VTG DRAM cell with the poly-Cap. and analyzed its device characteristics using TCAD simulations. Additionally, we evaluated the inference accuracy of the 2T DRAM-based PIM system using a customized simulation framework. We confirmed that the poly-Cap. increased the storage node capacitance by 31.9%, improved the retention characteristics by 83.3% and reduced the capacitive coupling effects by 52.4% during the write ‘1’ operation and 27.3% during the read ‘1’ operation.