Design of a 128-bit AES Block Cipher Processor on FPGA

Advanced Encryption Standard (AES), most widely used to encrypt or decrypt data, is computationally intensive application. In order to implement the AES encryption algorithm, the data must go through complicated operations composed of several steps. In this paper, we propose a 128-bit AES block cipher processor, which supports hardware based multi-processor scheduler for high performance computing system. The functionality of the AES processor was verified on FPGA along with a hardware scheduler.