TY - GEN
T1 - Design of a feasible on-chip interconnection network for a Chip Multiprocessor (CMP)
AU - Lee, Seung Eun
AU - Bahn, Jun Ho
AU - Bagherzadeh, Nader
PY - 2007
Y1 - 2007
N2 - In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switching technique and its routing algorithm is livelock-Zdeadlock- free in 2D-mesh topology. Major contribution of this research is the design of an adaptive router architecture adopting a minimal adaptive routing algorithm with near optimal performance and feasible design complexity, satisfying the general SoC design requirements. We also investigate the optimal size of FIFO in an adaptive router with fixed priority scheme.
AB - In this paper, an adaptive wormhole router for a flexible on-chip interconnection network is proposed and implemented for a Chip-Multi Processor (CMP). It adopts a wormhole switching technique and its routing algorithm is livelock-Zdeadlock- free in 2D-mesh topology. Major contribution of this research is the design of an adaptive router architecture adopting a minimal adaptive routing algorithm with near optimal performance and feasible design complexity, satisfying the general SoC design requirements. We also investigate the optimal size of FIFO in an adaptive router with fixed priority scheme.
UR - http://www.scopus.com/inward/record.url?scp=47249096169&partnerID=8YFLogxK
U2 - 10.1109/SBAC-PAD.2007.18
DO - 10.1109/SBAC-PAD.2007.18
M3 - Conference contribution
AN - SCOPUS:47249096169
SN - 9780769530147
T3 - Proceedings - Symposium on Computer Architecture and High Performance Computing
SP - 211
EP - 218
BT - Proceedings - 19th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD
T2 - 19th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD
Y2 - 24 October 2007 through 27 October 2007
ER -