@inproceedings{c6b7fee1c4a54ea18e6c9004ce8644af,
title = "Design of a Low-Jitter Digitally Controlled Oscillator With Supply Noise Compensation",
abstract = "This paper proposes a clock buffer with compensator technology to achieve low-jitter design in the digitally controlled oscillator (DCO). The compensator consists of a PMOS transistor and a MOS capacitor. The compensator that provides the opposite sensitivity to the delay cell is connected to the node between each delay cell. The compensated DCO has a reduced jitter of approximately 12.7-ps (peak-to-peak) based on the 3-GHz output frequency under ±0.1\% VDD noise.",
keywords = "Digital controlled oscillator(DCO), Supply noise compensation)",
author = "Kim, \{Min Ji\} and Lee, \{Won Young\}",
note = "Publisher Copyright: {\textcopyright} 2024 IEEE.; 2024 International Conference on Electronics, Information, and Communication, ICEIC 2024 ; Conference date: 28-01-2024 Through 31-01-2024",
year = "2024",
doi = "10.1109/ICEIC61013.2024.10457171",
language = "English",
series = "2024 International Conference on Electronics, Information, and Communication, ICEIC 2024",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2024 International Conference on Electronics, Information, and Communication, ICEIC 2024",
}