Design of a low-power 10-Bit 250-kS/s SAR ADC for neural recording applications

This paper presents a low-power 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) for neural recording applications. The proposed SAR ADC uses a modified V_CM-based switching scheme to reduce the switching power. In addition, asynchronous SAR logic operation is used to avoid using any internal high-speed clock generator. A calibration technique was realized for the comparator offset to enhance the accuracy of the SAR ADC. The ADC was designed using a standard 180-nm CMOS process, and its core area occupies only 0.15 mm². It operates at 250 kS/s with a 1-V supply voltage and consumes 4.2 μW. An ENOB of 9.72 and FoM of 19.92 fJ/conv-step were also achieved.