Design of an area-efficient hardware filter for embedded system

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2 Scopus citations

Abstract

In this paper, we propose an area-efficient hardware accelerated filter for embedded system. In order to minimize the area of hardware filter, the proposed filter architecture has a single multiplier. The filter operates by reusing the multiplier. In addition, we optimize the quantization bit length by analyzing the relationship between area and preciseness according to the quantization bit length. We verify the performance of the proposed filter by measuring frequency response in verification environment.

Original languageEnglish
Title of host publicationISOCC 2016 - International SoC Design Conference
Subtitle of host publicationSmart SoC for Intelligent Things
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages229-230
Number of pages2
ISBN (Electronic)9781467393089
DOIs
StatePublished - 27 Dec 2016
Event13th International SoC Design Conference, ISOCC 2016 - Jeju, Korea, Republic of
Duration: 23 Oct 201626 Oct 2016

Publication series

NameISOCC 2016 - International SoC Design Conference: Smart SoC for Intelligent Things

Conference

Conference13th International SoC Design Conference, ISOCC 2016
Country/TerritoryKorea, Republic of
CityJeju
Period23/10/1626/10/16

Keywords

  • Area-efficiency
  • Hardware filter
  • Quantization bit

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