Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

Sang Muk Lee; Ji Hoon Jang; Jung Hwan Oh; Ji Kwang Kim; Seung Eun Lee

doi:10.1587/elex.14.20170399

Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

Sang Muk Lee, Ji Hoon Jang, Jung Hwan Oh, Ji Kwang Kim, Seung Eun Lee

Electronic Engineering Program

Seoul National University of Science and Technology (SNUST)

Research output: Contribution to journal › Article › peer-review

19 Scopus citations

Abstract

Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65 nm CMOS technology.

Original language	English
Article number	20170399
Journal	IEICE Electronics Express
Volume	14
Issue number	11
DOIs	https://doi.org/10.1587/elex.14.20170399
State	Published - 2017

Keywords

Data compression
Hardware accelerator
High throughput
LZ4

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10.1587/elex.14.20170399

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Design of hardware accelerator for Lempel-Ziv 4 (LZ4) compression

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Keywords

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