TY - JOUR
T1 - Design of low-power clock generator synchronized with AC power for adiabatic dynamic CMOS logic
AU - Cho, Seung Il
AU - Kim, Seong Kweon
AU - Harada, Tomochika
AU - Yokoyama, Michio
PY - 2013/10/9
Y1 - 2013/10/9
N2 - To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197 μW and 58.1 μW at 3 kHz and 10 MHz, respectively.
AB - To reduce the power dissipation in conventional CMOS logic and to maintain adiabatic charging and discharging with low power for the adiabatic dynamic CMOS logic (ADCL), the clock signal of logic circuits should be synchronized with the AC power source. In this paper, the low-power clock generator synchronized with the AC power signal is proposed for ADCL system. From the simulation result, summation of power consumption of the designed wave shaping circuit (WSC) and asymmetry duty ratio divider (ADD) was estimated with approximately 1.197 μW and 58.1 μW at 3 kHz and 10 MHz, respectively.
KW - Adiabatic dynamic CMOS logic (ADCL)
KW - Asymmetry duty ratio divider (ADD)
KW - Low-power clock generator
KW - Synchronization
KW - Wave shaping circuit (WSC)
UR - http://www.scopus.com/inward/record.url?scp=84886528801&partnerID=8YFLogxK
U2 - 10.1587/elex.10.20130716
DO - 10.1587/elex.10.20130716
M3 - Article
AN - SCOPUS:84886528801
SN - 1349-2543
VL - 10
JO - IEICE Electronics Express
JF - IEICE Electronics Express
IS - 20
M1 - 20130716
ER -