Development of CMOS-Compatible Low Temperature Cu Bonding Optimized by the Response Surface Methodology

As an interconnect scaling in planar (2D) chips face a technical bottleneck, the vertically stacked structure called 3D integrated circuit (IC) packaging becomes a major packaging technology for the next generation heterogeneous integration. 3D IC packaging technology provides reduced interconnect lengths between the chips and improves electrical signal and power delivery problems. Among three core unit processes in 3D packaging, a wafer bonding process is still an immature process for mass production compared to through Si via formation and Si thinning. Most bonding materials used in stacked ICs so far are solder materials or Cu pillars with Sn cap, however with the demand of fine pitch less than 10um in a bonding layer, Cu bonding is of great interest in 3D IC heterogeneous packaging. Despite the excellent electrical and mechanical properties and fine pitch patternability, Cu bonding process has several challenges to be resolved, such as easy oxidation, high bonding temperature, extremely low dishing planarization and so on. In this study, the two-step plasma treatment method using Ar and N₂ was applied on the copper surface to achieve low temperature Cu bonding. N₂ plasma process of two-step plasma treatment was optimized by RSM (response surface methodology) based on CCD (central composite design) in DOE (design of experiment) system. With the optimized plasma treatment, the Cu bonding quality has been significantly improved compared to Cu bonding without any surface treatment at 300°C. Also, it has been demonstrated that the copper nitride passivation layer prevents further oxidation up to 1 week in air.