Dielectric glue wafer bonding and bonded wafer thinning for wafer-level 3D integration

J. Q. Lu, Y. Kwon, A. Jindal, J. J. McMahon, T. S. Cale, R. J. Gutmann

Research output: Contribution to conferencePaperpeer-review

7 Scopus citations

Abstract

Baseline processes established for 200 mm wafer bonding (using polymers as dielectric bonding glue) and bonded wafer thinning (using backgrinding, polishing, and etching) are presented, which are two critical processes in our approach to monolithic wafer-level 3D ICs. Four-point bending technique is used to quantify the bonding strength, identify the weak interface, and study their dependence on (1) glue thickness, (2) glue film preparation, and (3) materials and structures on the wafer(s). Mechanical and electrical properties of processed wafers with copper interconnect structures are preserved after wafer bonding and wafer thinning, confirming the potential of the bonding and thinning processes for 3D ICs.

Original languageEnglish
Pages76-86
Number of pages11
StatePublished - 2003

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