Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory

Munhyeon Kim; Kitae Lee; Sihyun Kim; Jong Ho Lee; Byung Gook Park; Daewoong Kwon

doi:10.1109/LED.2021.3116797

Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory

Munhyeon Kim, Kitae Lee, Sihyun Kim, Jong Ho Lee, Byung Gook Park, Daewoong Kwon

Dept. of Electrical and Information Engineering

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

In this letter, we propose a double-gated ferroelectric-gate field-effect-transistor (DG-FeFET) for processing-in-memory (PIM) operations in a single device for the first time. The proposed device is highly compatible with a conventional fin field-effect-transistor (FinFET) process and thus the scalable Fin FeFET with the completely sympatric double gates can be fabricated by adding only one gate metal recess process. After the rigorous calibrations of the ferroelectric and device technology computer aided design (TCAD) models by utilizing the fabricated ferroelectric capacitor and planar FeFET, it is demonstrated that the 16-Boolean logic operations including XNOR, NAND and AND can be stably implemented in a single DG-FeFET through energy-efficient two step operation scheme.

Original language	English
Pages (from-to)	1607-1610
Number of pages	4
Journal	IEEE Electron Device Letters
Volume	42
Issue number	11
DOIs	https://doi.org/10.1109/LED.2021.3116797
State	Published - 1 Nov 2021

Keywords

Boolean logics
ferroelectric-gate field-effect-transistor (FeFET)
Processing-in-memory (PIM)

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This output contributes to the following UN Sustainable Development Goals (SDGs)

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10.1109/LED.2021.3116797

Cite this

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title = "Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory",

abstract = "In this letter, we propose a double-gated ferroelectric-gate field-effect-transistor (DG-FeFET) for processing-in-memory (PIM) operations in a single device for the first time. The proposed device is highly compatible with a conventional fin field-effect-transistor (FinFET) process and thus the scalable Fin FeFET with the completely sympatric double gates can be fabricated by adding only one gate metal recess process. After the rigorous calibrations of the ferroelectric and device technology computer aided design (TCAD) models by utilizing the fabricated ferroelectric capacitor and planar FeFET, it is demonstrated that the 16-Boolean logic operations including XNOR, NAND and AND can be stably implemented in a single DG-FeFET through energy-efficient two step operation scheme.",

keywords = "Boolean logics, ferroelectric-gate field-effect-transistor (FeFET), Processing-in-memory (PIM)",

author = "Munhyeon Kim and Kitae Lee and Sihyun Kim and Lee, \{Jong Ho\} and Park, \{Byung Gook\} and Daewoong Kwon",

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doi = "10.1109/LED.2021.3116797",

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T1 - Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory

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AU - Lee, Kitae

AU - Kim, Sihyun

AU - Lee, Jong Ho

AU - Park, Byung Gook

AU - Kwon, Daewoong

PY - 2021/11/1

Y1 - 2021/11/1

N2 - In this letter, we propose a double-gated ferroelectric-gate field-effect-transistor (DG-FeFET) for processing-in-memory (PIM) operations in a single device for the first time. The proposed device is highly compatible with a conventional fin field-effect-transistor (FinFET) process and thus the scalable Fin FeFET with the completely sympatric double gates can be fabricated by adding only one gate metal recess process. After the rigorous calibrations of the ferroelectric and device technology computer aided design (TCAD) models by utilizing the fabricated ferroelectric capacitor and planar FeFET, it is demonstrated that the 16-Boolean logic operations including XNOR, NAND and AND can be stably implemented in a single DG-FeFET through energy-efficient two step operation scheme.

AB - In this letter, we propose a double-gated ferroelectric-gate field-effect-transistor (DG-FeFET) for processing-in-memory (PIM) operations in a single device for the first time. The proposed device is highly compatible with a conventional fin field-effect-transistor (FinFET) process and thus the scalable Fin FeFET with the completely sympatric double gates can be fabricated by adding only one gate metal recess process. After the rigorous calibrations of the ferroelectric and device technology computer aided design (TCAD) models by utilizing the fabricated ferroelectric capacitor and planar FeFET, it is demonstrated that the 16-Boolean logic operations including XNOR, NAND and AND can be stably implemented in a single DG-FeFET through energy-efficient two step operation scheme.

KW - Boolean logics

KW - ferroelectric-gate field-effect-transistor (FeFET)

KW - Processing-in-memory (PIM)

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Double-Gated Ferroelectric-Gate Field-Effect-Transistor for Processing in Memory

Abstract

Keywords

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