Dual-Gated ALD Oxide-Channel Nonvolatile Capacitive Memory Monolithically Integrated on Foundry 40-nm CMOS for Capacitive Digital Compute-in-Memory

In this work, we experimentally demonstrate monolithic 3-D (M3D) integration of dual-gated (DG) nonvolatile capacitive memory (nvCAP) featuring an ALD W-doped In2O3 (IWO) channel on a foundry 40-nm CMOS chip. We introduce a novel dual-gate engineering scheme for DG nvCAP, effectively addressing the weak erase and poor retention challenges in oxide-channel ferroelectrics (FEs). The BEOL-integrated DG nvCAP on the TSMC N40 CMOS chip achieves a capacitive ON-OFF ratio (CON/COFF) of ∼64.4 at Vread = 0 V-a record among reported BEOLcompatible nvCAPs. Furthermore, nondestructive read operation exceeding 109 stress cycles at jVreadj = 1 V is demonstrated in the same device. Finally, we introduce a new "capacitive"digital compute-in-memory (Cap-DCIM) paradigm, achieving 146× higher figure-of-merit (TOPS/W × TOPS/mm2) compared with leading analog compute-inmemories (ACIMs) and 111× lower static power versus SRAM-based DCIMs-enabled by highly scalable digital logic and BEOL integration of DG nvCAPs. We experimentally validate the operational principle of M3D Cap-DCIM by demonstrating BEOL capacitance-modulated FEOL Si transistor current amplification through monolithically integrated DG nvCAP on the TSMC N40 CMOS chip.