Abstract
Severe performance fluctuations and thus low worst-case performance are serious problems for NAND-based memory cards used as storage devices in portable consumer electronics. These problems are mainly caused by the erasebefore-write restriction of NAND flash memory. As the write to NAND is accumulated, a garbage collection is performed to reproduce clean blocks. The execution time of the garbage collection greatly depends on the association degree of the NAND blocks selected as victim. In other words, if the victim block has the high association degree, the execution time of the garbage collection becomes long, which adversely affects the overall performance of the memory card. To address this problem, this paper proposes a new hybrid mapping flash translation layer policy using dynamic active log pool, partial merge, and moving valid pages that reduce the association degree of victim blocks. The results of a trace-driven simulation show that the proposed policy reduces the worst-case latency of write requests by up to 44.8% compared to the best alternative policy. The average latency is also shortened by up to 4.1%.
| Original language | English |
|---|---|
| Article number | 8103381 |
| Pages (from-to) | 318-324 |
| Number of pages | 7 |
| Journal | IEEE Transactions on Consumer Electronics |
| Volume | 63 |
| Issue number | 3 |
| DOIs | |
| State | Published - Aug 2017 |
Keywords
- Flash translation layer
- Hybrid mapping
- Memory cards
- NAND flash memory
- Worst-case performance