TY - GEN
T1 - Evaluation of wafer level Cu bonding for 3D integration
AU - Kang, Sung Geun
AU - Kim, Youngrae
AU - Kim, Eun Sol
AU - Lim, Naeun
AU - Jeong, Teakgyu
AU - Lee, Jieun
AU - Kim, Sarah Eunkyung
AU - Kim, Sungdong
PY - 2011
Y1 - 2011
N2 - 3D wafer stacking [1-3] offers numerous opportunities such as memory stacking, logic stacking, heterogeneous device stacking, optical and RF interconnection, and system-on-chip. 3D integration can provide high performance, reduced cost, reduced size, and effective integration of divergent process flows. Wafer stacking is favored for a high volume manufacturing compared to chip to chip and chip to wafer processes. However, there are still many fabrication processes to be developed and reliability issues to be considered in order to implement wafer-to-wafer (W2W) stacking process.
AB - 3D wafer stacking [1-3] offers numerous opportunities such as memory stacking, logic stacking, heterogeneous device stacking, optical and RF interconnection, and system-on-chip. 3D integration can provide high performance, reduced cost, reduced size, and effective integration of divergent process flows. Wafer stacking is favored for a high volume manufacturing compared to chip to chip and chip to wafer processes. However, there are still many fabrication processes to be developed and reliability issues to be considered in order to implement wafer-to-wafer (W2W) stacking process.
UR - http://www.scopus.com/inward/record.url?scp=84866873288&partnerID=8YFLogxK
U2 - 10.1109/3DIC.2012.6263014
DO - 10.1109/3DIC.2012.6263014
M3 - Conference contribution
AN - SCOPUS:84866873288
SN - 9781467321891
T3 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
BT - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
T2 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Y2 - 31 January 2012 through 2 February 2012
ER -
