Evaluation of wafer level Cu bonding for 3D integration

Sung Geun Kang; Youngrae Kim; Eun Sol Kim; Naeun Lim; Teakgyu Jeong; Jieun Lee; Sarah Eunkyung Kim; Sungdong Kim

doi:10.1109/3DIC.2012.6263014

Evaluation of wafer level Cu bonding for 3D integration

Sung Geun Kang
, Youngrae Kim
, Eun Sol Kim
, Naeun Lim
, Teakgyu Jeong
, Jieun Lee
, Sarah Eunkyung Kim
, Sungdong Kim

Microsystem Packaging Center
Seoul National University of Science and Technology (SNUST)

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

2 Scopus citations

Abstract

3D wafer stacking [1-3] offers numerous opportunities such as memory stacking, logic stacking, heterogeneous device stacking, optical and RF interconnection, and system-on-chip. 3D integration can provide high performance, reduced cost, reduced size, and effective integration of divergent process flows. Wafer stacking is favored for a high volume manufacturing compared to chip to chip and chip to wafer processes. However, there are still many fabrication processes to be developed and reliability issues to be considered in order to implement wafer-to-wafer (W2W) stacking process.

Original language	English
Title of host publication	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
DOIs	https://doi.org/10.1109/3DIC.2012.6263014
State	Published - 2011
Event	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 - Osaka, Japan Duration: 31 Jan 2012 → 2 Feb 2012

Publication series

Name	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Conference

Conference	2011 IEEE International 3D Systems Integration Conference, 3DIC 2011
Country/Territory	Japan
City	Osaka
Period	31/01/12 → 2/02/12

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

SDG 9 Industry, Innovation, and Infrastructure

Access to Document

10.1109/3DIC.2012.6263014

Cite this

@inproceedings{2afd56fccd1c49f09fe33f9ad6910a82,

title = "Evaluation of wafer level Cu bonding for 3D integration",

abstract = "3D wafer stacking [1-3] offers numerous opportunities such as memory stacking, logic stacking, heterogeneous device stacking, optical and RF interconnection, and system-on-chip. 3D integration can provide high performance, reduced cost, reduced size, and effective integration of divergent process flows. Wafer stacking is favored for a high volume manufacturing compared to chip to chip and chip to wafer processes. However, there are still many fabrication processes to be developed and reliability issues to be considered in order to implement wafer-to-wafer (W2W) stacking process.",

author = "Kang, \{Sung Geun\} and Youngrae Kim and Kim, \{Eun Sol\} and Naeun Lim and Teakgyu Jeong and Jieun Lee and Kim, \{Sarah Eunkyung\} and Sungdong Kim",

year = "2011",

doi = "10.1109/3DIC.2012.6263014",

language = "English",

isbn = "9781467321891",

series = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011",

booktitle = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011",

note = "2011 IEEE International 3D Systems Integration Conference, 3DIC 2011 ; Conference date: 31-01-2012 Through 02-02-2012",

}

Kang, SG, Kim, Y, Kim, ES, Lim, N, Jeong, T, Lee, J, Kim, SE & Kim, S 2011, Evaluation of wafer level Cu bonding for 3D integration. in 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011., 6263014, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011, Osaka, Japan, 31/01/12. https://doi.org/10.1109/3DIC.2012.6263014

Evaluation of wafer level Cu bonding for 3D integration. / Kang, Sung Geun; Kim, Youngrae; Kim, Eun Sol et al.
2011 IEEE International 3D Systems Integration Conference, 3DIC 2011. 2011. 6263014 (2011 IEEE International 3D Systems Integration Conference, 3DIC 2011).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Evaluation of wafer level Cu bonding for 3D integration

AU - Kang, Sung Geun

AU - Kim, Youngrae

AU - Kim, Eun Sol

AU - Lim, Naeun

AU - Jeong, Teakgyu

AU - Lee, Jieun

AU - Kim, Sarah Eunkyung

AU - Kim, Sungdong

PY - 2011

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AB - 3D wafer stacking [1-3] offers numerous opportunities such as memory stacking, logic stacking, heterogeneous device stacking, optical and RF interconnection, and system-on-chip. 3D integration can provide high performance, reduced cost, reduced size, and effective integration of divergent process flows. Wafer stacking is favored for a high volume manufacturing compared to chip to chip and chip to wafer processes. However, there are still many fabrication processes to be developed and reliability issues to be considered in order to implement wafer-to-wafer (W2W) stacking process.

UR - https://www.scopus.com/pages/publications/84866873288

U2 - 10.1109/3DIC.2012.6263014

DO - 10.1109/3DIC.2012.6263014

M3 - Conference contribution

AN - SCOPUS:84866873288

SN - 9781467321891

T3 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

BT - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

T2 - 2011 IEEE International 3D Systems Integration Conference, 3DIC 2011

Y2 - 31 January 2012 through 2 February 2012

ER -

Evaluation of wafer level Cu bonding for 3D integration

Abstract

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Conference

UN SDGs

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