Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs

J. Q. Lu; A. Jindal; Y. Kwon; J. J. McMahon; M. Rasco; R. Augur; T. S. Cale; R. J. Gutmann

doi:10.1109/IITC.2003.1219717

Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs

J. Q. Lu, A. Jindal, Y. Kwon, J. J. McMahon, M. Rasco, R. Augur, T. S. Cale, R. J. Gutmann

Dept. of Chemical and Biomolecular Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

56 Scopus citations

Abstract

Electrical and mechanical impacts of wafer bonding and thinning processes required for three-dimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect processing. Promising results on wafers with oxide interlevel dielectric (ILD) have been obtained, while some damages observed with the porous low-k ILD.

Original language	English
Title of host publication	Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	74-76
Number of pages	3
ISBN (Electronic)	0780377974, 9780780377974
DOIs	https://doi.org/10.1109/IITC.2003.1219717
State	Published - 2003
Event	2003 IEEE International Interconnect Technology Conference, IITC 2003 - Burlingame, United States Duration: 2 Jun 2003 → 4 Jun 2003

Publication series

Name	Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

Conference

Conference	2003 IEEE International Interconnect Technology Conference, IITC 2003
Country/Territory	United States
City	Burlingame
Period	2/06/03 → 4/06/03

Keywords

Dielectrics
Fabrication
Glass
Inspection
Integrated circuit testing
Optical interconnections
Optical microscopy
Three-dimensional integrated circuits
Wafer bonding
Wet etching

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10.1109/IITC.2003.1219717

Cite this

Lu, J. Q., Jindal, A., Kwon, Y., McMahon, J. J., Rasco, M., Augur, R., Cale, T. S., & Gutmann, R. J. (2003). Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs. In Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003 (pp. 74-76). Article 1219717 (Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IITC.2003.1219717

Lu, J. Q. ; Jindal, A. ; Kwon, Y. et al. / Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs. Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. pp. 74-76 (Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003).

@inproceedings{dfabc32783e140f1b1c7c68ce56994fc,

title = "Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs",

abstract = "Electrical and mechanical impacts of wafer bonding and thinning processes required for three-dimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect processing. Promising results on wafers with oxide interlevel dielectric (ILD) have been obtained, while some damages observed with the porous low-k ILD.",

keywords = "Dielectrics, Fabrication, Glass, Inspection, Integrated circuit testing, Optical interconnections, Optical microscopy, Three-dimensional integrated circuits, Wafer bonding, Wet etching",

author = "Lu, {J. Q.} and A. Jindal and Y. Kwon and McMahon, {J. J.} and M. Rasco and R. Augur and Cale, {T. S.} and Gutmann, {R. J.}",

note = "Publisher Copyright: {\textcopyright} 2003 IEEE.; 2003 IEEE International Interconnect Technology Conference, IITC 2003 ; Conference date: 02-06-2003 Through 04-06-2003",

year = "2003",

doi = "10.1109/IITC.2003.1219717",

language = "English",

series = "Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "74--76",

booktitle = "Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003",

}

Lu, JQ, Jindal, A, Kwon, Y, McMahon, JJ, Rasco, M, Augur, R, Cale, TS & Gutmann, RJ 2003, Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs. in Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003., 1219717, Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003, Institute of Electrical and Electronics Engineers Inc., pp. 74-76, 2003 IEEE International Interconnect Technology Conference, IITC 2003, Burlingame, United States, 2/06/03. https://doi.org/10.1109/IITC.2003.1219717

Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs. / Lu, J. Q.; Jindal, A.; Kwon, Y. et al.
Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003. Institute of Electrical and Electronics Engineers Inc., 2003. p. 74-76 1219717 (Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › peer-review

TY - GEN

T1 - Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs

AU - Lu, J. Q.

AU - Jindal, A.

AU - Kwon, Y.

AU - McMahon, J. J.

AU - Rasco, M.

AU - Augur, R.

AU - Cale, T. S.

AU - Gutmann, R. J.

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AB - Electrical and mechanical impacts of wafer bonding and thinning processes required for three-dimensional (3D) IC fabrication have been evaluated with interconnect structures. In addition to the bonding and thinning required for a two-level 3D IC stack, an additional bonding and thinning process is used along with dielectric glue ashing to expose the previously tested interconnect structures. This procedure permits evaluation of bonding and thinning integrity without inter-wafer interconnect processing. Promising results on wafers with oxide interlevel dielectric (ILD) have been obtained, while some damages observed with the porous low-k ILD.

KW - Dielectrics

KW - Fabrication

KW - Glass

KW - Inspection

KW - Integrated circuit testing

KW - Optical interconnections

KW - Optical microscopy

KW - Three-dimensional integrated circuits

KW - Wafer bonding

KW - Wet etching

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BT - Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2003 IEEE International Interconnect Technology Conference, IITC 2003

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Lu JQ, Jindal A, Kwon Y, McMahon JJ, Rasco M, Augur R et al. Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs. In Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003. Institute of Electrical and Electronics Engineers Inc. 2003. p. 74-76. 1219717. (Proceedings of the IEEE 2003 International Interconnect Technology Conference, IITC 2003). doi: 10.1109/IITC.2003.1219717

Evaluation procedures for wafer bonding and thinning of interconnect test structures for 3D ICs

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