Abstract
Device variation is a fundamental challenge for analog compute-in-memory (ACIM) systems. Instead of treating it as an error, we strategically exploit it as a source of computational diversity. We harness this natural process-induced variation by programming two low-precision deep neural network (DNN) replicas onto the same ACIM chip. A soft-voting mechanism then aggregates their outputs for a more robust prediction. To quantify the system-level trade-offs, we extend the NeuroSim V1.4 framework to co-evaluate accuracy, area, latency, and energy. On VGG-8/CIFAR-10, as the conductance variation σ increases from 0.05 to 0.25, the accuracy gain of the 4-bit ensemble over its 4-bit single-model (SM) counterpart grows from 0.46 to 3.05 percentage points (pp). Notably, at σ =0.05, the ensemble even surpasses the zero-variation baseline by 0.303 pp. Compared to an 8-bit SM baseline, the 4-bit ensemble becomes comparable to or surpasses it for σ ≥ 0.10, achieving up to 1.28 pp at σ=0.25. Hardware evaluation using an SRAM-based ACIM architecture shows that the two-replica ensemble achieves a 9.0% smaller chip area than the 8-bit baseline, at the cost of 30% higher latency and 2.1% higher energy. We further observe consistent accuracy-overhead trends for RRAM- and FeFET-based ACIM under their respective nonideality characteristics.
| Original language | English |
|---|---|
| Pages (from-to) | 1889-1901 |
| Number of pages | 13 |
| Journal | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
| Volume | 34 |
| Issue number | 6 |
| DOIs | |
| State | Published - 1 Jun 2026 |
Keywords
- Analog compute-in-memory (ACIM)
- FeFET
- RRAM
- SRAM
- conductance variation
- ensemble learning
- weight quantization
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