TY - GEN
T1 - Fabrication of Multi-RDL Layers with Polymeric IDL for RDL Interposer
AU - Jang, Jinho
AU - Kang, Minji
AU - Kim, Injoo
AU - Lee, Siye
AU - Jin, Hyein
AU - Kim, Sungdong
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - The application of heterogeneous integration as a structural platform for next-generation semiconductors has led to extensive exploration of 2.x D package technologies, such as silicon interposers, bridges, and RDL interposers. RDL interposers consist of metal wiring layers (redistribution layer, RDL) and insulating layers (inter layer dielectric, ILD). One of the key challenges in fabricating RDL interposers is the planarization of the ILD. This paper presents the development of a planarization process for multilayer RDL interposers by the utilization of a pressing method with a plate. To determine the level of planarization, we employed the Degree of Planarization (DOP) and conducted measurements using a surface profiler. The specimens were fabricated to have 3.5μm thick Cu RDL covered by 7μm thick PI (HD-4100) ILD on Si wafers. The pressing method was applied during the soft bake process of the ILD. We used scanning electron microscope (SEM) to observe the cross-sectional profiles of the specimens with and without the pressing method. The pressing method improved the degree of planarization (DOP) of the ILD, as confirmed by both surface profiler measurements and SEM analysis. The results demonstrate that the pressing technique is an effective approach to enhance the flatness of RDL interposers, which is critical for the reliable fabrication of multilayer structures.
AB - The application of heterogeneous integration as a structural platform for next-generation semiconductors has led to extensive exploration of 2.x D package technologies, such as silicon interposers, bridges, and RDL interposers. RDL interposers consist of metal wiring layers (redistribution layer, RDL) and insulating layers (inter layer dielectric, ILD). One of the key challenges in fabricating RDL interposers is the planarization of the ILD. This paper presents the development of a planarization process for multilayer RDL interposers by the utilization of a pressing method with a plate. To determine the level of planarization, we employed the Degree of Planarization (DOP) and conducted measurements using a surface profiler. The specimens were fabricated to have 3.5μm thick Cu RDL covered by 7μm thick PI (HD-4100) ILD on Si wafers. The pressing method was applied during the soft bake process of the ILD. We used scanning electron microscope (SEM) to observe the cross-sectional profiles of the specimens with and without the pressing method. The pressing method improved the degree of planarization (DOP) of the ILD, as confirmed by both surface profiler measurements and SEM analysis. The results demonstrate that the pressing technique is an effective approach to enhance the flatness of RDL interposers, which is critical for the reliable fabrication of multilayer structures.
UR - https://www.scopus.com/pages/publications/105001338154
U2 - 10.1109/EPTC62800.2024.10909842
DO - 10.1109/EPTC62800.2024.10909842
M3 - Conference contribution
AN - SCOPUS:105001338154
T3 - Proceedings of the 26th Electronics Packaging Technology Conference, EPTC 2024
SP - 501
EP - 504
BT - Proceedings of the 26th Electronics Packaging Technology Conference, EPTC 2024
A2 - Shin, Sunmi
A2 - Toh, Chin Hock
A2 - Lim, Yeow Kheng
A2 - Chidambaram, Vivek
A2 - Chui, King Jien
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 26th Electronics Packaging Technology Conference, EPTC 2024
Y2 - 3 December 2024 through 6 December 2024
ER -